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參數(shù)資料
| 型號： | sda 9205 |
| 廠商： | SIEMENS AG |
| 英文描述： | Triple 8-Bit Analog-to-Digital-Converter(三倍8位A/D轉(zhuǎn)換器) |
| 中文描述： | 三8位模擬到數(shù)字轉(zhuǎn)換器（三倍8位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 20/31頁 |
| 文件大?。?/td> | 560K |
| 代理商： | SDA 9205 |
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SDA 9205-2
Semiconductor Group
20
Output Coding for Binary/Two’s Complement Mode
Binary or two’s complement output coding is selectable for each separate output port (A, B, C) via
control inputs DTA, DTB, DTC. This coding is independent from selected formats (8:8:8, 8:4:4,
8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1).
Table 1
Output Coding for Formats 8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1
Table 1 is valid for
V
REFL
= 0.5 V and
V
REFH
= 2.5 V
V
CA
V
CB, C
= ext. clamping level during CLAMP high pulse at
C
ext cl
on channel AINB and AINC.
In output format 4:2:2 a special suppression of code 0 and code 255 is provided in the binary output
mode.
= ext. clamping level during CLAMP high pulse at
C
ext cl
on channel AINA.
Step
VIN
Converter
A
<
V
CA
– 0.125 V
V
CA
– 0.125 V
V
CA
– 0.117 V
.
.
.
.
V
CA
+ 1.867 V
V
CA
+ 1.875 V
>
V
CA
+ 1.875 V
VIN
Converter
B, C
<
V
CB, C
– 1 V
V
CB, C
– 1 V
V
CB, C
– 0.992 V
.
.
.
.
V
CB, C
+ 0.992 V
V
CB, C
+ 1 V
>
V
CB, C
+ 1 V
OFL
Bit
UFL
Bit
Binary
Output
7 6 5 4 3 2 1 0
Two’s
Complement
7 6 5 4 3 2 1 0
Underflow
0
1
.
.
.
.
254
255
Overflow
0
0
0
.
.
.
.
.
0
1
1
0
0
.
.
.
.
.
0
0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
.
.
.
.
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1
.
.
.
.
0 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
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