參數(shù)資料
型號(hào): sda 9205
廠商: SIEMENS AG
英文描述: Triple 8-Bit Analog-to-Digital-Converter(三倍8位A/D轉(zhuǎn)換器)
中文描述: 三8位模擬到數(shù)字轉(zhuǎn)換器(三倍8位的A / D轉(zhuǎn)換器)
文件頁(yè)數(shù): 25/31頁(yè)
文件大?。?/td> 560K
代理商: SDA 9205
SDA 9205-2
Semiconductor Group
25
Figure 5
Timing Diagram Port A, B, C
Timing (see figure 5)
Output data delay time
t
QD
t
QH
t
WH
;
t
WL
t
TLH
t
THL
t
SU
t
IH
t
Ci
25
ns
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
1 nF ext. clamp cap.
Output data hold time
6
ns
CLK pulse width
10
ns
CLK rise time
5
ns
CLK fall time
5
ns
Input data setup time
7
ns
Input data hold time
6
ns
Clamp input pulse width
10
CLK
cycles
Characteristics
(cont’d)
V
DD
= 5 V
±
5 %,
V
CC
= 5 V
±
5 %,
V
REFH
= 2.5 V,
V
REFL
= 0.5 V,
V
GND
= 0 V
f
CLK
= 27 MHz, all specifications min (
T
A
) to max (
T
A
) unless otherwise noted
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
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