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參數(shù)資料
| 型號： | SCANSTA111MT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 524K |
| 代理商： | SCANSTA111MT |
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State Machines
(Continued)
Following a hardware reset, the TAP controller state-
machine is in the
Test-Logic-Reset
(TLR) state; the ’STA111-
selection state-machine is in the
Wait-For-Address
state;
and each of the three port-selection state-machines is in the
Parked-TLR
state. The ’STA111 is then ready to receive
Level-1 protocol, followed by Level-2 protocol.
Tester/SCANSTA111 Interface
An IEEE 1149.1 system tester sends instructions to a
’STA111 via that ’STA111’s backplane scan-port. Following
test logic reset, the ’STA111’s selection state-machine is in
the
Wait-For-Address
state. When the ’STA111’s TAP con-
troller is sequenced to the
Shift-IR
state, data shifted in
through the TDI
input is shifted into the ’STA111’s instruc-
tion register. Note that prior to successful selection of a
’STA111, data is not shifted out of the instruction register and
out through the ’STA111’s TDO
output, as it is during nor-
mal scan operations. Instead, as each new bit enters the
instruction register’s most-significant bit, data shifted out
from the least-significant bit is discarded.
When the instruction register is updated with the address
data, the ’STA111’s address-recognition logic compares the
seven least-significant bits of the instruction register with the
7-bit assigned address which is statically present on the
S
inputs. Simultaneously, the scanned-in address is
compared with the reserved Broadcast and Multi-cast ad-
dresses. If an address match is detected, the ’STA111-
selection state-machine enters one of the two selected
states. If the scanned address does not match a valid single-
slot address or one of the reserved broadcast/multi-cast
addresses, the ’STA111-selection state-machine enters the
Unselected
state.
Note that the SLOT inputs should not be set to a value
corresponding to a multi-cast group, or to the broadcast
address. Also note that the single ’STA111 selection process
must be performed for all ’STA111s which are subsequently
to be addressed in multi-cast mode. This is required be-
cause each such device’s Multicast Group Register (MCGR)
must be programmed with a multi-cast group number, and
the MCGR is not accessible to the test controller until that
’STA111 has first entered the
Selected-Single-’STA111
state.
Once a ’STA111 has been selected, Level-2 protocol is used
to issue commands and to access the chip’s various regis-
ters.
Register Set
The SCANSTA111 includes a number of registers which are
used for ’STA111 selection and configuration, scan data
manipulation, and scan-support operations. These registers
can be grouped as shown in
Table 3
.
The specific fields and functions of each of these registers
are detailed in the section of this document titled Data Reg-
ister Descriptions.
Note that when any of these registers is selected for inser-
tion into the ’STA111’s scan-chain, scan data enters through
that register’s most-significant bit. Similarly, data that is
shifted out of the register is fed to the scan input of the
next-downstream device in the scan-chain.
TABLE 3. Register Descriptions
Register Name
Instruction Register
BSDL Name
INSTRUCTION
Description
STA111 addressing and instruction-decode IEEE Std. 1149.1 required
register
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 optional register
STA111-group address assignment
STA111 local-port configuration and control bits
STA111 local-port configuration and control bits (Note 5)
STA111 Shared GPIO configuration bits
STA111 scan-data compaction (signature generation)
Boundary-Scan Register
Bypass Register
Device Identification Register
Multi-Cast Group Register
Mode Register
0
Mode Register
1
Mode Register
2
Linear-Feedback Shift
Register
TCK Counter Register
Dedicated GPIO Register
(0-n)
Shared GPIO Register
(0-n)
BOUNDARY
BYPASS
IDCODE
MCGR
MODE
(TBD)
(TBD)
LFSR
CNTR
(TBD)
(TBD)
Local-port TCK clock-gating (for BIST)
STA111 Dedicated GPIO control bits (Note 6)
STA111 Shared GPIO control bits (Note 6)
Note 5:
One dedicated and one shared GPIO register exists for each LSP that supports dedicated and/or shared GPIO (maximum of eight shared and eight
dedicated GPIO registers).
Note 6:
HDL version only
S
www.national.com
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCANSTA112 | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| SCANSTA112SM | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| SCANSTA112VS | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| SCANSTA476 | Eight Input IEEE 1149.1 Analog Voltage Monitor |
| SCANSTA476TSD | Eight Input IEEE 1149.1 Analog Voltage Monitor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANSTA111MT/NOPB | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA111MT/NOPB | 制造商:Texas Instruments 功能描述:, Termination:Solder, Package/Case:48-TS |
| SCANSTA111MTX | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA111MTX/NOPB | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA111SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
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