
Special Features
TRANSPARENT MODE
While this mode is activated, the selected LSP n ports will
follow the backplane ports. TRST
is a buffered version of
TRST
B
, TCK
n
is a buffered version of TCK
B
, TMS
n
is a
buffered version of TMS
B
, TDO
n
is a buffered version of TDI
B
and TDO
B
is a buffered version of TDI
n
. TRIST
B
and TRIST
n
are asserted when the state machine is in either the
Shift-DR
or
Shift-IR
states. The unselected LSPs are placed in the
PARKTLR
state, and their clocks are gated after 512 TCK
B
clock cycles.
Transparent Mode is controlled by 8 new instructions,
TRANSPARENT0
through
TRANSPARENT7
. Transparent
Mode overrides any other active mode. When one of the
transparent mode instruction is shifted into the instruction
register and the tap controller goes through the
UPDATE-IR
state, TRST
will go high, and TMS
n
will go low. This will
force the targets connected to the LSP
ports to go into the
RTI
state. Then as the STA111 state machine goes into the
RTI
state, all of the LSP
signals will follow the back-plane
signals. This is identical to the method that is typically used
to unpark an LSP. The STA111 will remain in this mode until
a TRST
is asserted or a power cycle forces a reset. Once in
the Transparent Mode, the STA111 will not be able to be
reset by a 5 TMS high reset.
The sequence of operations to use Transparent Mode on an
LSP are as follows (example uses LSP
0
):
1.
IR-Scan the STA111 address into the instruction register
(address a STA111).
2.
IR-Scan the
TRANSPARENT0
instruction to enable
Transparent Mode on LSP
0
. Transparent Mode is en-
abled when the TAP enters the
RTI
state at the end of
this shift operation (TRST
0
, TDO
0
, TMS
0
and TCK
0
be-
come buffered versions of TRST
B
, TDI
B
, TMS
B
and
TCK
B
and TDO
B
becomes a buffered version of TDI
0
).
NOTE: Transparent Mode will persist until the STA111 is
reset using TRST
B
. The
GOTOWAIT
and
SOFTRESET
instructions will not work in this mode.
BIST SUPPORT
The sequence of instructions to run BIST testing on a parked
SCANSTA111 port is as follows:
1.
Pre-load the Boundary register of the device under test if
needed.
2.
Issue the
CNTRSEL
instruction and initialize (load) the
TCK counter to 00000000 Hex. Note that the TCK
counter is initialized to 00000000 Hex upon
Test-Logic-
Reset
, so this step may not be necessary.
3.
Issue the
CNTRON
instruction to the ’STA111, to enable
the TCK counter.
4.
Shift the
PARKRTI
instruction into the ’STA111 instruc-
tion register and
BIST
instruction into the instruction
register of the device under test. With the counter on (at
terminal count) and the LSP parked, the local TCK is
gated.
5.
Issue the
CNTRSEL
instruction to the ’STA111.
6.
Load the TCK counter (Shift the 32-bit value represent-
ing the number of TCK
cycles needed to execute the
BIST operation into the TCK counter register). The Self
test will begin on the rising edge of TCK
B
following the
Update-DR
TAP controller state.
Bit 7 of Mode Register
can be scanned to check the
status of the TCK counter, (
MODESEL
instruction fol-
lowed by a
Shift-DR
). Bit 7 logic 0 means the counter
has not reached terminal count, logic 1 means that the
counter has reached terminal count and the BIST opera-
tion has completed.
Execute the
CNTROFF
instruction.
Unpark the LSP and scan out the result of the BIST
operation
7.
8.
9.
RESET
Reset operations can be performed at three levels. The
highest level resets all ’STA111 registers and all of the local
scan chains of selected and unselected ’STA111s. This Level
1 reset is performed whenever the ’STA111 TAP Controller
enters the
Test-Logic-Reset
state.
Test-Logic-Reset
can be
entered synchronously by forcing TMS
high for at least five
(5) TCK
pulses, or asynchronously by asserting the TRST
B
pin. A Level 1 reset forces all ’STA111s into the
Wait-For-
Address
state, parks all local scan chains in the
Test-Logic-
Reset
state, and initializes all ’STA111 registers.
The
SOFTRESET
instruction is provided to perform a Level
2 reset of all LSP’s of selected ’STA111s.
SOFTRESET
forces all TMS
signals high, placing the corresponding local
TAP Controllers in the
Test-Logic-Reset
state within five (5)
TCK
B
cycles.
The third level of reset is the resetting of individual local
ports. An individual LSP can be reset by parking the port in
the
Test-Logic-Reset
state via the
PARKTLR
instruction. To
reset an individual LSP that is parked in one of the other
parked states, the LSP must first be unparked via the
UN-
PARK
instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of the
four TAP Controller states:
Test-Logic-Reset
,
Run-Test/Idle
,
Pause-DR
, or
Pause-IR
. The ’STA111 is able to park a local
chain by controlling the local Test Mode Select outputs
(TMS
) (see
Figure 4
). TMS
is forced high for parking in
the
Test-Logic-Reset
state, and forced low for parking in
Run-Test/Idle
,
Pause-IR
, or
Pause-DR
states. Local chain
access is achieved by issuing the
UNPARK
instruction. The
LSPs do not become unparked until the ’STA111 TAP Con-
troller is sequenced through a specified synchronization
state. Synchronization occurs in the
Run-Test/Idle
state for
LSPs parked in
Test-Logic-Reset
or
Run-Test/Idle
; and in the
Pause-DR
or
Pause-IR
state for ports parked in
Pause-DR
or
Pause-IR
, respectively.
Figure 11
and
Figure 12
show the waveforms for synchroni-
zation of a local chain that was parked in the
Test-Logic-
Reset
state. Once the
UNPARK
instruction is received in the
instruction register, the LSPC forces TMS
n
low on the falling
edge of TCK
B
.
S
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