參數(shù)資料
型號(hào)： SCANSTA111MT
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48
封裝： TSSOP-48
文件頁(yè)數(shù)： 21/29頁(yè)
文件大?。?/td> 524K
代理商： SCANSTA111MT
Special Features
(Continued)
Number/Type of GPIO bits:
The STA111 has both dedi-
cated and shared GPIO (General Purpose I/O). Each
dedicated group of GPIO bits supports from 0 to 4 dedi-
cated inputs and 0 to 4 dedicated outputs. There are
provisions for specifying the default (power-up) value.
TMS
, TDO
and TDI
are also dual purpose
pins functioning as LSP or GPIO. TMS
and TDO
n
are
outputs, TDI
n
is an input in the GPIO mode.
Throught this datasheet, notations exist to clarify the differ-
ences between features available on the Silicon version and
the HDL version.
KNOWN POWER-UP STATE
The STA111 has a known power-up condition. This is the
same state that the device is in after a TRST reset. This
happens at power-up without the presence of a TCK
B
.
Reset can also occur via a 5 TMS high reset or a
SOFTRE-
SET
command.
POWER-OFF HIGH IMPEDANCE INPUTS AND
OUTPUTS
The STA111 backplane test port features power-off high
impedance inputs and outputs.
The TDI
B
, TMS
B
, and TRST
B
inputs have a 25K
pull-up
resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
DD
float-
ing), these inputs appear to be a capacitive load to ground.
When V
DD
= 0V (i.e.; not floating but tied to V
SS
) these inputs
appear to be capacitive with the pull-up to ground.
The TCK
B
input has no pull-up resistor and no ESD clamp
diode (ESD is controlled with an alternate method). When
the device is power-off (V
floating), the input appears to be
a capacitive load to ground. When V
= 0V (i.e.; not floating
but tied to V
SS
) the input appears to be a capacitive load to
ground.
When the device is power-off (V
= 0V or floating), the
TDO
B
output appears to be a capacitive load.
Refer to the device IBIS model on our website for more
details
about
the
I/O
www.national.com/appinfo/scan/ibis.html.
characteristics
at
http://
TRST
TRST
B
:
Assertion of TRST
B
will return the device back to its
known power-up state.
TRST
n
:
TRST
is an output on the LSP side of the STA111.
While the LSP state-machine (level 2 protocol) is in the
Parked-TLR
state the TRST
pin will be driven low. In all
other states the TRST
n
pin will be driven high.
PHYSICAL LAYER CHANGES
TRIST for TDO
B
and TDO
n
are signals for enabling an
external buffer circuit between the ’STA111 and the
backplane/LSP. This would allow, for example, a CMOS-to-
LVDS converter to drive an LVDS JTAG backplane test bus.
These signals are always driving. A seperate TRIST is pro-
vided for each LSP to report a TRI-STATE on TDO when the
LSP is not in a shift state.
SVF DRIVEN, SELF-CHECKING TEST BENCH
The STA111 consists of 3 types of pins, dot1 backplane pins,
dot1 LSP pins and support pins. The command interpreter of
the test bench is able to translate a limited set of SVF
commands to the dot1 backplane pins. The SVF shift com-
mands contain both the stimulus (TDI
B
) and expected re-
sponse (TDO
B
).
The interpreter is able to parse the following commands:
ENDDR
,
ENDIR
,
RUNTEST
,
SDR
,
SIR
,
STATE
,
TRST
.
PASS-THROUGH PINS
Each LSP may selectively have two pass-through pins. The
pair of pass-through pins consist of an input (A
n
) and an
output (Y
n
). The LSP pass-through output (Y
n
) drives the
level being received by the backplane pass-through input
(A
B
). Conversly, the level on the LSP pass-through input (A
n
)
drives the backplane pass-through output (Y
B
).
The Pass-through pins are available only when a single LSP
is selected. For each LSP these pins will be enabled when
the level 2 protocol state-machine is not in the
Parked-TLR
state. When not enabled they are TRI-STATED.
LSP GATING
While the LSP state-machine (level 2 protocol) is in the
Parked-TLR
state, the four LSP signals shall be controlled
as shown in
Table 14
below. Upon entry into the
Parked-TLR
state (
power-up
,
reset
,
PARKTLR
or
GOTOWAIT
) a counter
in the LSP state-machine allows 512 TCK
clock pulses to
occur on TCK
n
before gating. Once gated, TCK
n
will drive a
logic 0.
Letting 512 TCK
pulses pass through to TCK
allows a five
high TMS reset to occur on over 100 levels of hierarchy
before the STA111 gates TCK
n
(for power saving in a free-
running clock system).
TABLE 14. Gated LSP Drive States
LSP
Connection
TDO
n
TMS
n
TDI
n
TCK
n
Drive State
Pull-up resistor to provide a weak HIGH
Pull-up resistor to provide a weak HIGH
Pull-up resistor to provide a weak HIGH
TCK
B
for 512 pulses, then gated LOW
The STA111 does not require that any clock pulses are
received on TCK
B
while in the
Parked-TLR
state.
Setting Bit 3 of Mode Register
0
to 1 gates TCK
n
when in the
Parked-RTI
,
Parked-Pause-DR
states. Default is free-running (bit 3 = 0). The value stored in
bit 3 of Mode Register
0
does not effect the requirement of
512 clock pulses before gating TCK
n
in the
Parked-TLR
state. (See section on Mode Register
0
).
and
Parked-Pause-IR
IEEE 1149.4 SUPPORT
The STA111 provides support for a switched analog bus.
Each
LSP
has
an
unparked-TLR
(LSP_ACTIVE
) which is low (0) when the LSP is in
Parked-TLR
and high (1) otherwise. This signal can be used
to enable/disable analog switches external to the STA111.
notification
pin
GPIO CONNECTIONS
General Purpose I/O (GPIO) pins are registered inputs and
outputs that are parameterized in the HDL. The two types of
GPIOs than can be used in the STA111 are described in the
next two sections.
DEDICATED:
Each LSP supports up to four (4) dedicated
inputs and up to four (4) dedicated outputs. These are sep-
erate, dedicated GPIO signals controlled by dedicated GPIO
S
www.national.com
21
相關(guān)PDF資料
PDF描述
SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer
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SCANSTA112VS 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer
SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor
SCANSTA476TSD Eight Input IEEE 1149.1 Analog Voltage Monitor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SCANSTA111MT/NOPB 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA111MT/NOPB 制造商:Texas Instruments 功能描述:, Termination:Solder, Package/Case:48-TS
SCANSTA111MTX 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA111MTX/NOPB 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
SCANSTA111SM 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
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