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參數(shù)資料
| 型號(hào)： | SCAN162512ASM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | SCAN/JTAG/3J SERIES, DUAL 8-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PBGA64 |
| 封裝： | BGA-64 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 163K |
| 代理商： | SCAN162512ASM |
Connection Diagram
20075303
Top View
See NS Package Number SLC64A
Truth Table
Function Table (Note 1)
Inputs
Outputs
OEAB
LEAB
CLKAB
A
B
LL
L
X
B
0 (Note 2)
LL
↑
LL
↑
HH
LH
X
L
LH
X
H
XXX
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 1: A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions were established.
Functional Description
In the normal mode, these devices are 16-bit universal bus
transceivers that combine D-type latches and D-type flip-
flops to allow data flow in transparent, latched, or clocked
modes. They can be used as two 8-bit transceivers, or as
one 16-bit transceiver. The test circuitry can be activated by
the TAP to take snapshot samples of the data appearing at
the device pins or to perform a self test on the boundary-test
cells. Activating the TAP may affect the normal functional
operation of the universal bus transceivers. When the TAP is
activated, the test circuitry performs boundary-scan test op-
erations according to the protocol described in IEEE Std
1149.1-1990.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
devices operate in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched while CLKAB is held
at a static low or high logic level. Otherwise, if LEAB is low,
A data is stored on a low-to-high transition of CLKAB. When
OEAB is LOW, the B outputs are active. When OEAB is
HIGH, the B outputs are in the high-impedance state. B-to-A
data flow is similar to A-to-B data flow but uses the OEBA,
LEBA, and CLKBA inputs.
Five dedicated test pins are used to observe and control the
operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), test clock (TCK), and
test reset (TRST). All testing and scan operations are syn-
chronized to the TAP interface.
For details about the sequence of boundary scan cells in the
SCAN16512A, please refer to the BSDL (Boundary Scan
Description Language) file available on our website.
SCAN16512A
www.national.com
3
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| SCAN162512ASM/NOPB | 功能描述:IC UNIV BUS TXRX 16BIT 64FBGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:SCAN 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動(dòng)器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
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| SCAN162602SM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver with TRI-STATE-R Outputs |
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