參數(shù)資料
型號： SC9RS08KA1J3CDB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO6
封裝： 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, DFN-6
文件頁數(shù)： 73/134頁
文件大小： 3114K
代理商： SC9RS08KA1J3CDB
Chapter 5 Resets, Interrupts, and General System Control
SC9RS08KA2 Series Data Sheet, Rev. 1
Freescale Semiconductor
43
5.8.5
System Power Management Status and Control 1 Register
(SPMSC1)
This high page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ACMP and the LVD module.
Figure 5-6. System Power Management Status and Control 1 Register (SPMSC1)
76
54
321
0
RLVDF
0
LVDIE
LVDRE(1)
1 This bit can be written only one time after reset. Additional writes are ignored.
LVDSE
LVDE(1)
0
BGBE
W
LVDACK
Reset:
000
11
100
= Unimplemented or Reserved
Table 5-8. SPMSC1 Register Field Descriptions
Field
Description
7
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This write-once bit enables low-voltage detect events to generate a
hardware reset (provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ACMP module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
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