參數(shù)資料
型號： SC9RS08KA1J3CDB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO6
封裝： 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, DFN-6
文件頁數(shù)： 106/134頁
文件大小： 3114K
代理商： SC9RS08KA1J3CDB
Chapter 8 Central Processor Unit (RS08CPUV1)
SC9RS08KA2 Series Data Sheet, Rev. 1
Freescale Semiconductor
73
Table 8-2. Opcode Map
DIR
TNY
DIR/REL
INH
TNY
SRT
IMM/INH
DIR/EXT
SRT
0
1
2345
678
9
A
B
C
D
E
F
0
5
BRSET0
3DIR
5
BSET0
2DIR
4
INC
1TNY
3
BRA
2REL
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
SUB
2IMM
3
SUB
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
1
5
BRCLR0
3DIR
5
BCLR0
2DIR
4
INC
1TNY
5
CBEQ
3DIR
4
CBEQA
3IMM
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
CMP
2IMM
3
CMP
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
2
5
BRSET1
3DIR
5
BSET1
2DIR
4
INC
1TNY
1
SLA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
SBC
2IMM
3
SBC
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
3
5
BRCLR1
3DIR
5
BCLR1
2DIR
4
INC
1TNY
1
COMA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
4
5
BRSET2
3DIR
5
BSET2
2DIR
4
INC
1TNY
3
BCC
2REL
1
LSRA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
AND
2IMM
3
AND
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
5
5
BRCLR2
3DIR
5
BCLR2
2DIR
4
INC
1TNY
3
BCS
2REL
1
SHA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
6
5
BRSET3
3DIR
5
BSET3
2DIR
4
INC
1TNY
3
BNE
2REL
1
RORA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
LDA
2IMM
3
LDA
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
7
5
BRCLR3
3DIR
5
BCLR3
2DIR
4
INC
1TNY
3
BEQ
2REL
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
3
STA
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
8
5
BRSET4
3DIR
5
BSET4
2DIR
4
INC
1TNY
1
CLC
1INH
1
LSLA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
EOR
2IMM
3
EOR
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
9
5
BRCLR4
3DIR
5
BCLR4
2DIR
4
INC
1TNY
1
SEC
1INH
1
ROLA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
ADC
2IMM
3
ADC
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
A
5
BRSET5
3DIR
5
BSET5
2DIR
4
INC
1TNY
5
DEC
2DIR
1
DECA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
ORA
2IMM
3
ORA
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
B
5
BRCLR5
3DIR
5
BCLR5
2DIR
4
INC
1TNY
6
DBNZ
3DIR
4
DBNZA
2INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2
ADD
2IMM
3
ADD
2DIR
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
C
5
BRSET6
3DIR
5
BSET6
2DIR
4
INC
1TNY
5
INC
2DIR
1
INCA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
1
NOP
1INH
4
JMP
3EXT
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
D
5
BRCLR6
3DIR
5
BCLR6
2DIR
4
INC
1TNY
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
3
BSR
2REL
4
JSR
3EXT
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
E
5
BRSET7
3DIR
5
BSET7
2DIR
4
INC
1TNY
4
MOV
3IMD
5
MOV
3DD
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2+
STOP
1INH
3
RTS
1INH
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
F
5
BRCLR7
3DIR
5
BCLR7
2DIR
4
INC
1TNY
3
CLR
2DIR
1
CLRA
1INH
4
DEC
1TNY
3
ADD
1TNY
3
SUB
1TNY
2
CLR
1SRT
2
CLR
1SRT
2+
WAIT
1INH
5+
BGND
1INH
3
LDA
1SRT
3
LDA
1SRT
2
STA
1SRT
2
STA
1SRT
INH
Inherent
REL
Relative
IMM
Immediate
SRT
Short
DIR
Direct
TNY
Tiny
EXT
Extended
DD
Direct-Direct
IMD
Immediate-Direct
High Byte of Opcode in Hexadecimal
B
Gray box is decoded as illegal instruction
Low Byte of Opcode in Hexadecimal
0
3
SUB
2DIR
RS08 Cycles
Opcode Mnemonic
Number of Bytes /
Addressing Mode
LOW
HIGH
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