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9397 750 14963
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2005
5 of 46
Philips Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
D0 to D7
44, 45,
46, 47,
48, 1, 2,
3
39, 20
I/O
Data bus (bi-directional).
These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
DSRA, DSRB
I
Data Set Ready (active LOW).
These inputs are associated with individual UART
Channel A and Channel B. A logic 0 (LOW) on these pins indicates the modem or data
set is powered-on and is ready for data exchange with the UART. The state of these
inputs is reflected in the Modem Status Register (MSR).
Data Terminal Ready (active LOW).
These outputs are associated with individual
UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates that the
SC68C752B is powered-on and ready. These pins can be controlled via the modem
control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW),
enabling the modem. The output of these pins will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset.
Signal and power ground.
Interrupt Request.
Interrupts from UART Channel A and Channel B are wire-ORed
internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled
by the interrupt enable register) whenever a UART channel(s) requires service.
Individual channel interrupt status can be determined by addressing each channel
through its associated internal register, using CS and A3. An external pull-up resistor
must be connected between this pin and V
CC
.
A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an
external CPU to an internal register that is defined by address bits A[0:2]. A logic HIGH
on this pin will load the contents of an internal register defined by address bits A[0:2] on
the SC68C752B data bus (D[0:7]) for access by an external CPU.
Not connected.
DTRA, DTRB
34, 35
O
GND
IRQ
17, 24
30
I
O
R/W
15
I
n.c.
12, 25,
29, 37
32, 9
-
OPA, OPB
O
User defined outputs.
This function is associated with individual Channel A and
Channel B. The state of these pins is defined by the user through the software settings
of MCR[3]. OPA/OPB is a logic 0 when MCR[3] is set to a logic 1. OPA/OPB is a logic 1
when MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
Reset (active LOW).
This pin will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during reset time.
RESET is an active LOW input.
Ring Indicator (active LOW).
These inputs are associated with individual UART
Channel A and Channel B. A logic 0 on these pins indicates the modem has received a
ringing signal from the telephone line. A LOW-to-HIGH transition on these input pins
generates a modem status interrupt, if enabled. The state of these inputs is reflected in
the Modem Status Register (MSR).
Request to Send (active LOW).
These outputs are associated with individual UART
Channel A and Channel B. A logic 0 on the RTS pin indicates the transmitter has data
ready and waiting to send. Writing a logic 1 in the Modem Control Register MCR[1] will
set this pin to a logic 0, indicating data is available. After a reset these pins are set to a
logic 1. These pins only affect the transmit and receive operations when Auto-RTS
function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow
control operation.
Receive data input.
These inputs are associated with individual serial channel data to
the SC68C752B. During the local loop-back mode, these RX input pins are disabled
and TX data is connected to the UART RX input internally.
RESET
36
I
RIA, RIB
41, 21
I
RTSA, RTSB
33, 22
O
RXA, RXB
5, 4
I
Table 2:
Symbol
Pin description
…continued
Pin
Type
Description