參數(shù)資料
型號(hào): SC68C752B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola mP interface
中文描述: 5伏,3.3伏和2.5伏兆5雙UART /秒(最大),64字節(jié)的FIFO和摩托羅拉手機(jī)接口
文件頁(yè)數(shù): 26/46頁(yè)
文件大?。?/td> 219K
代理商: SC68C752B
9397 750 14963
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2005
26 of 46
Philips Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
mode, data set, or peripheral device to the processor. It also indicates when a control
input from the modem changes state.
Table 16
shows modem status register bit settings
per channel.
[1]
The primary inputs RI, CD, CTS, DSR are all active LOW, but their registered equivalents in the MSR and
MCR (in loop-back) registers are active HIGH.
Table 16:
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
[1]
CD (active HIGH, logical 1). This bit is the complement of the CD input during
normal mode. During internal loop-back mode, it is equivalent to MCR[3].
MSR[6]
[1]
RI (active HIGH, logical 1). This bit is the complement of the RI input during
normal mode. During internal loop-back mode, it is equivalent to MCR[2].
MSR[5]
[1]
DSR (active HIGH, logical 1). This bit is the complement of the DSR input
during normal mode. During internal loop-back mode, it is equivalent MCR[0].
MSR[4]
[1]
CTS (active HIGH, logical 1). This bit is the complement of the CTS input
during normal mode. During internal loop-back mode, it is equivalent to
MCR[1].
MSR[3]
CD. Indicates that CD input (or MCR[3] in loop-back mode) has changed
state. Cleared on a read.
MSR[2]
RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed state
from LOW to HIGH. Cleared on a read.
MSR[1]
DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has changed
state. Cleared on a read.
MSR[0]
CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has changed
state. Cleared on a read.
6
5
4
3
2
1
0
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