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參數(shù)資料
| 型號： | SC660EYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SMBus System Clock Buffer for Mobile Applications |
| 中文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 57K |
| 代理商： | SC660EYB |
SC660E
SMBus System Clock Buffer for Mobile Applications
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134. Tel: 408-043-2600
http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002
Page 3 of 8
2-Wire SMBus Control Interface
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-
addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-
wire control interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to
indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a
data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first
byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address
D2
by generating the acknowledge (low)
signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface
conditions. Previously set control registers are retained.
Serial Control Registers
NOTE:
The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “
Command Code
“
byte, and
2) “
Byte Count
” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte
0, Byte 1, Byte2, ....) will be valid and acknowledged.
Byte 0: Function Select Register (
1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
-
-
7
6
3
2
Description
reserved
reserved
reserved
reserved
SDRAM3 (Active = 1, Forced low = 0)
SDRAM2 (Active = 1, Forced low = 0)
SDRAM1 (Active = 1, Forced low = 0)
SDRAM0 (Active = 1, Forced low = 0)
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