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參數(shù)資料
| 型號(hào)： | SC660EYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | SMBus System Clock Buffer for Mobile Applications |
| 中文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 57K |
| 代理商： | SC660EYB |
SC660E
SMBus System Clock Buffer for Mobile Applications
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134. Tel: 408-043-2600
http://www.cypress.com
Document#: 38-07025 Rev. *A
12/17/2002
Page 2 of 8
Pin Description
PIN
No.
9
Pin
Name
FIN
PWR
I/O
TYPE
Description
-
I
PAD
This pin is connected to the input reference clock. This clock
must be in the range of 10.0 to 100.0 Mhz.
Low skew output clocks.
2,3,6,7,1
1,18,22,2
3,26,27
20
SDRAM(0:9)
VDDB
O
BUF1
OE
-
I
PAD
Buffer Output Enable pin. This pin is low it is used to place
all output clocks (CLK1:10) in a tri state condition. This
feature facilitates in production board level testing to be
easily implemented for the clocks that this device produces.
Has internal pull-up resistor.
Serial Data for SMBus control interface. This pin receives
data streams from the SMBus bus and outputs an
acknowledge for valid data.
Serial Clock for SMBus control interface.
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
14
SDATA
VDD
I/O
PAD
15
SCLOCK
VSS
VDD
I
PAD
-
4, 8, 12,
16, 17,
21, 25
1, 5, 10,
19, 24,
28
13
PWR
VDDB
-
PWR
-
Power for output clock buffers.
VDD
-
PWR
-
Pin for device core logic.
Maximum Ratings
1
1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
-65oC to + 150oC
-40oC to +85oC
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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