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參數(shù)資料
| 型號： | SC418ULTRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 24/30頁 |
| 文件大?。?/td> | 691K |
| 描述： | IC REG DL BUCK/LINEAR 20MLPQ |
| 產(chǎn)品培訓模塊： | Power Supplies 101 |
| 標準包裝： | 1 |
| 系列： | EcoSpeed® |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 1MHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 0.75 V ~ 5.25 V，200mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-MLPQ |
| 供應(yīng)商設(shè)備封裝： | 20-MLPQ（3x3） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC418ULTRTDKR |
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SC418
24
Applications Information (continued)
meet the two design criteria of minimum 379礔 and
maximum 9m& ESR, select two capacitors rated at 220礔
and 5m& ESR.
It is recommended that an additional small capacitor be
placed in parallel with C
OUT
in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect opera-
tion. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 0mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also impera-
tive to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small capacitor across the upper feedback resistor, as
shown in Figure 4. This capacitor should be left unpopu-
lated unless it can be confirmed that double-pulsing
exists. Adding the C
TOP
capacitor will couple more ripple
into FB to help eliminate the problem. An optional con-
nection on the PCB should be available for this capacitor.
V
OUT
To FB pin
R2
R1
C
TOP
Figure 14 Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resis-
tance in the high current output path. A side effect of
adding trace resistance is decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
0mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insuffi-
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
charging during the switching cycle. For most applica-
tions the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
sw
OUT
MIN
f
C
2
3
SR
E
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
virtual ESR network composed of two capacitors and one
resistor, as shown in Figure 5.
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