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參數(shù)資料
| 型號(hào)： | SC418ULTRT |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 17/30頁(yè) |
| 文件大?。?/td> | 691K |
| 描述： | IC REG DL BUCK/LINEAR 20MLPQ |
| 產(chǎn)品培訓(xùn)模塊： | Power Supplies 101 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | EcoSpeed® |
| 拓?fù)洌?/td> | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開(kāi)關(guān)： | 1MHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 0.75 V ~ 5.25 V，200mA |
| 帶 LED 驅(qū)動(dòng)器： | 無(wú) |
| 帶監(jiān)控器： | 無(wú) |
| 帶序列發(fā)生器： | 無(wú) |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-MLPQ |
| 供應(yīng)商設(shè)備封裝： | 20-MLPQ（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱(chēng)： | SC418ULTRTDKR |
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SC418
7
FB
threshold
High-side
Drive (DH)
Low-side
rive (DL)
V
OUT
drifts up to due to leakage
current flowing into C
OUT
DH and DL off
DL turns on when Smart
SAVE threshold is reached
mart Power Save
hreshold (550mV)
DL turns off when FB
Single DH on-time pulse
after DL turn-off
V
OUT
discharges via inductor
and low-side MOSFET
Normal DL pulse after DH
on-time pulse
Normal V
OUT
ripple
Figure 7 Smart Power-Save
SmartDrive
TM
For each DH pulse, the DH driver initially turns on the
high-side MOSFET at a slower speed, allowing a softer,
smooth turn-off of the low-side diode. Once the diode is
off and the LX voltage has risen 0.5V above PGND, the
SmartDrive circuit automatically drives the high-side
MOSFET on at a rapid rate. This technique reduces switch-
ing noise while maintaining high efficiency, reducing the
need for snubbers or series resistors in the gate drive.
Enable Input for Switching Regulator
The EN input is a logic level input. When EN is low
(grounded), the switching regulator is off and in its lowest
power state. When EN is low and VDDA is above the VDDA
UVLO threshold, the output of the switching regulator
soft-discharges into the VOUT pin through an internal
5& resistor. When EN is a logic high (>V) the switching
regulator is enabled.
The EN input has internal resistors 2M& pullup to
VDDA, and a M& pulldown to AGND. These resistors will
normally cause the EN voltage to be near the logic high
trip point as VDDA reaches the VDDA UVLO threshold.
To prevent undesired toggling of EN and erratic startup
performance, the EN pin should not be allowed to float as
open-circuit.
Note that the LDO enable pin (ENL) can also disable the
switching regulator through the V
IN
UVLO function. Refer
to the ENL Pin and V
IN
UVLO section.
Current Limit Protection
The SC48 features programmable current limiting, which
is accomplished using the RDS
(ON)
of the lower MOSFET for
current sensing. The current limit is set by R
ILIM
resistor
which connects from the ILIM pin to the drain of the low-
side MOSFET. When the low-side MOSFET is on, an internal
0糀 current flows from the ILIM pin and through the R
ILIM
resistor, creating a voltage drop across the resistor. While
the low-side MOSFET is on, the inductor current flows
through it and creates a voltage across the RDS
(ON)
. The
voltage across the MOSFET is negative with respect to
PGND. If this MOSFET voltage drop exceeds the voltage
across R
ILIM
, the voltage at the ILIM pin will be negative and
current limit will activate. The current limit then keeps the
low-side MOSFET on and prevents another high-side on-
time, until the current in the low-side MOSFET reduces
enough to bring the I
LIM
voltage up to zero. This method
regulates the inductor valley current at the level shown by
I
LIM
in Figure 8.
Time
I
PEAK
I
LOAD
I
LIM
Figure 8 Valley Current Limit
The current limit schematic with the R
ILIM
resistor is shown
in Figure 9.
Applications Information (continued)
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