參數(shù)資料
型號(hào)： SC26C92
廠商： NXP Semiconductors N.V.
英文描述： Dual universal asynchronous receiver/transmitter (DUART）(雙通用異步接收器/傳送器)
中文描述： 雙路通用異步接收器/發(fā)送器（杜阿爾特）（雙通用異步接收器/傳送器）
文件頁(yè)數(shù)： 15/31頁(yè)
文件大?。?/td> 203K
代理商： SC26C92
Philips Semiconductors
Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
15
Table 2. Register Bit Formats
(Continued)
BIT 7
BIT 6
FRAMING
ERROR*
0 = No
1 = Yes
BIT 5
PARITY
ERROR*
0 = No
1 = Yes
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
0 01
0x01
RECEIVED
BREAK*
0 = No
1 = Yes
OVERRUN
ERROR
0 = No
1 = Yes
TxEMT
TxRDY
FFULL
RxRDY
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE:
*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits
(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are
discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using
the error reset command (command 4x) or a receiver reset.
BIT 7
OP7
BIT 6
OP6
BIT 5
OP5
BIT 4
OP4
BIT 3 BIT 2
OP3
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1X)
11 = RxCB(1X)
BIT 1 BIT 0
OP2
00 = OPR[2]
01 = TxCA(16X)
10 = TxCA(1X)
11 = RxCA(1X)
O C
OPCR
0x0D
0 = OPR[7]
1 = TxRDYB
0 = OPR[6]
1 = TxRDYA
0 = OPR[5]
1 = RxRDY/
FFULLB
0 = OPR[4]
1 = RxRDY/
FFULLA
SOPR
0x0E
BIT 7
See Note
BIT 6
See Note
BIT 5
See Note
BIT 4
See Note
BIT 3
See Note
BIT 2
See Note
BIT 1
See Note
BIT 0
See Note
NOTE:
0 = No Change; 1 = Set
ROPR
0x0F
BIT 7
See Note
BIT 6
See Note
BIT 5
See Note
BIT 4
See Note
BIT 3
See Note
BIT 2
See Note
BIT 1
See Note
BIT 0
See Note
NOTE:
0 = No Change; 1 = Reset
BIT 7
OP 7
BIT 6
OP 6
BIT 5
OP 5
BIT 4
OP 4
BIT 3
OP 3
BIT 2
OP 2
BIT 1
OP 1
BIT 0
OP 0
OPR
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
0 = Pin High
1 = Pin Low
BIT 7
BRG SET
SELECT
0 = set 1
1 = set 2
BIT 6 BIT 5 BIT 4
COUNTER/TIMER
MODE AND SOURCE
BIT 3
DELTA
IP 3 INT
0 = Off
1 = On
BIT 2
DELTA
IP 2 INT
0 = Off
1 = On
BIT 1
DELTA
IP 1 INT
0 = Off
1 = On
BIT 0
DELTA
IP 0 INT
0 = Off
1 = On
ACR
0x04
See Table 6
BIT 7
DELTA
IP 3
0 = No
1 = Yes
BIT 6
DELTA
IP 2
0 = No
1 = Yes
BIT 5
DELTA
IP 1
0 = No
1 = Yes
BIT 4
DELTA
IP 0
0 = No
1 = Yes
BIT 3
BIT 2
BIT 1
BIT 0
IPCR
0x04
IP 3
IP 2
IP 1
IP 0
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
BIT 7
INPUT
PORT
CHANGE
0 = No
1 = Yes
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ISR
0x05
DELTA
BREAK B
RxRDY/
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDY/
FFULLA
TxRDYA
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
BIT 7
IN. PORT
CHANGE
INT
0 = Off
1 = On
BIT 6
DELTA
BREAK B
INT
0 = Off
1 = On
BIT 5
RxRDY/
FFULLB
INT
0 = Off
1 = On
BIT 4
BIT 3
BIT 2
DELTA
BREAK A
INT
0 = Off
1 = On
BIT 1
RxRDY/
FFULLA
INT
0 = Off
1 = On
BIT 0
IMR
0x05
TxRDYB
INT
COUNTER
READY
INT
0 = Off
1 = On
TxRDYA
INT
0 = Off
1 = On
0 = Off
1 = On
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