
Philips Semiconductors
Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
13
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved
registers at addresses H‘02’ and H‘0A’ should never be read during
normal operation since they are reserved for internal diagnostics.
Table 1.
SC26C92 Register Addressing
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ (RDN = 0)
WRITE (WRN = 0)
Mode Register A (MR0A, MR1A, MR2A)
Status Register A (SRA)
Reserved
Rx Holding Register A (RxFIFOA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Value (CTU)
Counter/Timer Lower Value (CTL)
Mode Register B (MR0B, MR1B, MR2B)
Status Register B (SRB)
Reserved
Rx Holding Register B (RxFIFOB)
User Defined Flag/Status Flag
Input Ports IP0 to IP6
Start Counter Command
Stop Counter Command
Mode Register A (MR0A, MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (TxFIFOA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Value (CTPU)
C/T Lower Preset Value (CTPL)
Mode Register B (MR0B, MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (TxFIFOB)
User Defined Flag/Status Flag
Output Port Conf. Register (OPCR)
Set Output Port Bits Command (SOP12)
Reset Output Port Bits Command (ROP12)
NOTE:
The three MR Registers are accessed via the MR Pointer and Commands 1xh and Bxh. (Where “x” represents receiver and transmitter enable/
disable control)
The following named registers are the same for Channels
A and B
Mode Register
MRnA
Status Register
Clock Select
CSRA
Command Register
CRA
Receiver FIFO
RxFIFOA
Transmitter FIFO
TxFIFOA
MRnB
SRB
CSRB
CRB
RxFIFOB
TxFIFOB
R/W
R only
W only
W only
R only
W only
SRA
These registers control the functions which service both
Channels
Input Port Change Register
Auxiliary Control Register
Interrupt Status Register
Interrupt Mask Register
Counter Timer Upper Value
Counter Timer Lower Value
Counter Timer Preset Upper
Counter Timer Preset Lower
Input Port Register
Output Configuration Register
Set Output Port Bits
Reset Output Port Bits
IPCR
ACR
ISR
IMR
CTU
CTL
CTPU
CTPL
IPR
OPCR
SOPR
ROPR
R
W
R
W
R
R
W
W
R
W
W
W
Table 2.
Register Bit Formats
BIT 7
BIT 6
BIT 5
TxINT (1:0)
BIT 4
BIT 3
DON’T
CARE
Set to 0
BIT 2
BIT 1
TEST 2
BIT 0
MR0A, MR0B
MR0B[3:0] are
reserved
Returns F on read
d
Rx WATCH
DOG
0 = Disable
1 = Enable
RxINT BIT 2
BAUD RATE
EXTENDED II
0 = Normal
1 = Extend II
BAUD RATE
EXTENDED 1
0 = Normal
1 = Extend
See Tables in
MR0 description
Returns 1 on read
Set to 0
BIT 7
BIT 6
Rx INT
BIT 1
BIT 5
ERROR
MODE
BIT 4 BIT 3
BIT 2
PARITY
TYPE
BIT 1 BIT 0
BITS PER
CHARACTER
00 = 5
01 = 6
10 = 7
11 = 8
MR1A
MR1B
0x00
Rx CONTROLS
RTS
PARITY MODE
0 = No
1 = Yes
0 = RxRDY
1 = FFULL
0 = Char
1 = Block
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
0 = Even
1 = Odd
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.