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參數(shù)資料
| 型號(hào)： | SC2463TSTRT |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 18/23頁(yè) |
| 文件大?。?/td> | 459K |
| 描述： | IC REG QD BCK/LINEAR 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（2），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 4 |
| 頻率 - 開(kāi)關(guān)： | 600kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 電壓/電流 - 輸出 3： | 控制器 |
| 帶 LED 驅(qū)動(dòng)器： | 無(wú) |
| 帶監(jiān)控器： | 無(wú) |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 4.5 V ~ 30 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1358 (CN2011-ZH PDF) |
| 其它名稱： | SC2463TSDKR |
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18
?2007 Semtech Corp.
www.semtech.com
SC2463
POWER MANAGEMENT
Applications Information (Cont.)
Where, T is switching cycle period.
Because the inductor current ramps up according to Vin
Vo, and down with Vo, a falling output voltage in over
current condition moves the inductor ramp up cur-
rent up faster and the peak current I
P
larger but the
ramp down current slower. As long as the current is
still larger than the current limiting threshold, the top
switch is held off. The switching frequency is folded back
lower but average current is still relatively high.
An example is shown in Typical Characteristics section
with input voltage 12V and output voltage 5V with out-
put current 3.5A.
The preset valley current limit is 5A, which has to be
greater than full load current 3.5A. When the output is
shorted, the inductor peak current and the load current,
both are a function of the input voltage and the output
inductance, would be higher than the current limit. There-
fore, proper thermal management and inductor satura-
tion current rating have to be considered at the worst
conditions.
Loop Compensation
Loop Compensation
Loop Compensation
Loop Compensation
Loop Compensation
SC2463 is a voltage mode buck controller with high gain
bandwidth error amplifier utilizing external network com-
pensation to regulate output voltage.
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high crossover frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
The power stage of a buck converter control-to-output
transfer function is as shown below:
LC
s
R
L
s
1
C
sR
1
V
)
s
(
G
2
C
IN
VD
+
+
+
=
where,
LC
1
O
=
?/DIV>
L - Output inductance
C - Output capacitance
R
C
- Output capacitor ESR
V
IN
- Input voltage
The transfer function of the error amplifier with external
compensation network is as follows:
)
s
1
)(
s
1
(
)
s
1
)(
s
1
(
s
)
s
(
G
2
P
1
P
2
Z
1
Z
I
COMP
?/DIV>
+
?/DIV>
+
?/DIV>
+
?/DIV>
+
?/DIV>
?/DIV>
=
referring to Fig. 7, where,
2
3
1
2
Z
1
2
1
Z
C
)
R
R
(
1
,
C
R
1
+
=
?/DIV>
=
?/DIV>
3
1
3
1
2
2
P
2
3
1
P
3
1
1
I
C
C
C
C
R
1
,
C
R
1
,
)
C
C
(
R
1
+
=
?/DIV>
=
?/DIV>
+
=
?/DIV>
R3
C3
R2
R1
C1
Vref
C2
-
+
Figure 7. Voltage Mode Buck Converter Compensation
Network
With the compensation, the converter total loop gain is
as follows:
C
L
s
R
L
s
1
C
R
1
s
1
s
1
s
1
s
1
s
1
s
V
V
1
)
s
(
G
)
s
(
G
G
)
s
(
T
1
2
1
4
C
2
P
2
Z
1
P
1
Z
I
I
M
VD
COMP
PWM
+
+
?/DIV>
+
?/DIV>
?/DIV>
+
?/DIV>
?/DIV>
+
?/DIV>
?/DIV>
+
?/DIV>
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
?/DIV>
?/DIV>
=
Where:
G
PWM
= PWM gain
V
M
= 3.0V, ramp peak to valley voltage of SC2463
The design guidelines are as follows:
1. Set the loop gain crossover frequency ?/SPAN>
C
less than
1/5th the switching frequency.
2. Place an integrator in the origin to increase DC and
low frequency gains.
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