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參數(shù)資料
| 型號： | SC2463TSTRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 459K |
| 描述： | IC REG QD BCK/LINEAR 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 拓撲： | 降壓（降壓）同步（2），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 4 |
| 頻率 - 開關(guān)： | 600kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 電壓/電流 - 輸出 3： | 控制器 |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 4.5 V ~ 30 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1358 (CN2011-ZH PDF) |
| 其它名稱： | SC2463TSDKR |
16
?2007 Semtech Corp.
www.semtech.com
SC2463
POWER MANAGEMENT
Applications Information (Cont.)
.
f
V
I
)
1
)(
t
t
(
P
s
in
o
2
f
r
2
1
ts
?/DIV>
+
+
=
where t
r
is the rise time and t
f
is the fall time of the
switching process. Different manufactures have different
definitions and test conditions for t
r
and t
f
. To clarify
these, we sketch the typical MOSFET switching
characteristics under clamped inductive mode in Figure
6.
Figure 6. MOSFET switching characteristics
Where,
Q
gs1
is the gate charge needed to bring the gate-to-source
voltage V
gs
to the threshold voltage V
gs_th
,
Q
gs2
is the additional gate charge required for the switch
current to reach its full-scale value I
ds
.
and
Q
gd
is the charge needed to charge gate-to-drain (Miller)
capacitance when V
ds
is falling.
Switching losses occur during the time interval [t
1
, t
3
].
Defining t
r
= t
3
-t
1
and t
r
can be approximated as
.
V
V
R
)
Q
Q
(
t
gsp
cc
gt
gd
2
gs
r
+
=
where R
gt
is the total resistance from the driver supply
rail to the gate of the MOSFET. It includes the gate driver
internal impedance R
gi
, external resistance R
ge
and the
gate resistance R
g
within the MOSFET i.e.
R
gt
= R
gi
+R
ge
+R
g
.
V
gsp
is the Miller plateau voltage shown in Figure 11.
Similarly an approximate expression for t
f
is
.
V
R
)
Q
Q
(
t
gsp
gt
gd
2
gs
f
+
=
Only a portion of the total losses P
g
= Q
g
V
cc
f
s
is dissipated
in the MOSFET package. Here Q
g
is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
.
f
V
Q
R
R
P
s
cc
g
gt
g
tg
=
The total power loss of the top switch is then
P
t
= P
tc
+P
ts
+P
tg
.
If the input supply of the power converter varies
over a wide range, then it will be necessary to weigh
the relative importance of conduction and switching
losses. This is because conduction losses are inversely
proportional to the input voltage. Switching loss how-
ever increases with the input voltage. The total power
loss of MOSFET should be calculated and compared for
high-line and low-line cases. The worst case is then
used for thermal design.
Bottom Switch:
The RMS current in bottom switch can be shown to be
.
)
1
)(
D
1
(
I
I
12
o
rms
,
2
Q
2
?/DIV>
+
=
The conduction losses are then
P
bc
=I
Q2,rms
2
R
ds(on)
.
where R
ds(on)
is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
V
in
=12V, V
o
=1.5V), the duty ratio D will be small. Since
the bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFETs, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
terminals. The switching loss
s
d
o
2
f
r
2
1
bs
f
V
I
)
1
)(
t
t
(
P
?/DIV>
+
+
=
is negligible due to near zero-voltage switching.
The gate losses are estimated as
.
f
V
Q
R
R
P
s
cc
g
gt
g
bg
=
The total bottom switch losses are then
P
b
=P
bc
+P
bs
+P
bg
.
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