參數(shù)資料
型號(hào): SC16C752
廠商: NXP Semiconductors N.V.
英文描述: Dual UART with 64-byte FIFO
中文描述: 雙UART具有64字節(jié)FIFO
文件頁數(shù): 1/47頁
文件大?。?/td> 604K
代理商: SC16C752
SC16C752
Dual UART with 64-byte FIFO
Rev. 04 — 20 June 2003
Product data
1.
Description
The SC16C752 is a dual universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to
5 Mbits/s (3.3 V and 5 V). The SC16C752 offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C752 is available in a plastic LQFP48 package.
2.
Features
I
Pin compatible with SC16C2550 with additional enhancements
I
Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbits/s)
I
64-byte transmit FIFO
I
64-byte receive FIFO with error flags
I
Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
I
Software/hardware flow control
N
Programmable Xon/Xoff characters
N
Programmable auto-RTS and auto-CTS
I
Optional data flow resume by Xon any character
I
DMA signalling capability for both received and transmitted data
I
Supports 5 V, 3.3 V and 2.5 V operation
I
Software selectable baud rate generator
I
Prescaler provides additional divide-by-4 function
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