
AMD Geode SC1200/SC1201 Processor Data Book
421
Electrical Specifications
Revision 7.1
Figure 9-25. Register Transfer to/from Device Timing Diagram
ADDR valid1
WRITE
READ
t0
t1
t2
t9
t2i
t3
t5
t6z
t6
tA
t4
tC
tRD
tB
tC
IDE_IOR0#
IDE_IOW0#
IDE_IORDY02,3
IDE_IORDY02,4
IDE_IORDY02,5
Notes:
1)
Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0].
2)
Negation of IDE_IORDY0,1 is used to extend the PIO cycle. The determination of whether or not the cycle is to be
extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.
3)
Device never negates IDE_IORDY[0:1]. Device keeps IDE_IORDY[0:1] released, and no wait is generated.
4)
Device negates IDE_IORDY[0:1] before tA but causes IDE_IORDY[0:1] to be asserted before tA. IDE_IORDY[0:1] is
released, and no wait is generated.
5)
Device negates IDE_IORDY[0:1] before tA. IDE_IORDY[0:1] is released prior to negation and may be asserted for no
more than 5 ns before release. A wait is generated.
6)
The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1] is
asserted, the device places read data on IDE_DATA[15:0] for tRD before asserting IDE_IORDY[0:1].
IDE_DATA[7:0]