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| 型號(hào)： | SC1201UFH-266 |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA481 |
| 封裝： | 40 X 40 MM, 2.38 MM HEIGHT, 1.27 MM PITCH, MS-034BAU1, TEPBGA-481 |
| 文件頁(yè)數(shù)： | 266/465頁(yè) |
| 文件大?。?/td> | 4068K |
| 代理商： | SC1201UFH-266 |
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338
AMD Geode SC1200/SC1201 Processor Data Book
Video Processor Module
Revision 7.1
Weave
The Weave method assembles the odd field and even field
together to form the complete frame, and then renders the
“weaved” frames to the display device. The Video data is
converted from interlaced to progressive. Since both fields
are rendered simultaneously, the GX1 module’s video
frame buffer must be at least double buffered. The Weave
method has the advantage of not creating the temporal
effects that Bob does. The disadvantage of Weave is twice
as much data is transferred from the video frame buffer to
the Video Processor; meaning that Weave uses more
memory bandwidth.
Figure 7-6 on page 339 is an example of the Weave
method in action. As in the Bob example (Figure 7-5), a
CRT monitor at 85 Hz refresh is assumed. Double buffering
of the incoming data is also assumed. The example does
not assume anything about any scaling that may be done in
the Video Processor. No attempt has been made to assure
that this example is absolutely workable. The example is
only presented to allow for a general understanding of how
the SC1200/SC1201 processor’s video support hardware
works.
The following procedure is an example of how to create the
Weave method. Since at least double buffering is required,
more of the VIP’s control registers are used for Weave than
required for Bob during video runtime.
1)
Program the VIP bus master address registers.
Three registers control where the VIP video data is
stored in the GX1 module’s frame buffer:
– F4BAR2+Memory Offset 20h – Video Data Odd
Base Address
– F4BAR2+Memory Offset 24h – Video Data Even
Base Address
– F4BAR2+Memory Offset 28h – Video Data Pitch
The Video Data Even Base Address must be sepa-
rated from the Video Data Odd Base Address by one
horizontal line. The Video Data Pitch register must be
programmed to one horizontal line.
2)
Program other VIP bus master support registers.
Ensure the VIP FIFO Bus Request Threshold is set to
32 bytes (F4BAR2+Memory Offset 00h[22] = 1) and
the Video Input Port mode is set to CCIR-656
(F4BAR2+Memory Offset 00h[1:0] = 10). An interrupt
needs to be generated so that the GX1 module’s video
frame buffer pointer can flip to the field that has com-
pleted transfer to the video frame buffer. So the Field
Interrupt bit (F4BAR2+Memory Offset 04h[16] = 1).
must
be
enabled.
Auto-Flip
is
normally
set
(F4BAR2+Memory Offset 04h[10] = 0) to allow the
CCIR-656 decoder to identify which field is being pro-
cessed. Capture video data needs to be enabled
(F4BAR2+Memory Offset 04h[10] = 1) and Run Mode
Capture is set to Start Capture (F4BAR2+Memory Off-
set 04h[1:0] = 11) at beginning of next field. Data is
now being captured to the frame buffer.
3)
Field Interrupt.
When the field interrupt occurs on the completion of an
odd field, the interrupt must program the Video Data
Odd Base Address with the other buffer’s address. The
odd field will ping-pong between the two buffers. When
the interrupt is due to the completion of an even field,
the interrupt handler must program the GX1 module’s
video buffer start offset value (GX_BASE+Memory
Offset 8320h) with the address of the frame (both odd
and even fields) that was just received from the VIP
block. This new address will not take affect until the
start of a new frame. It must also program the Video
Data Even Base Address with the other buffer so that
the even field will ping-pong just like the odd field. The
field just received can be known by reading the Cur-
rent Field bit (F4BAR2+Memory Offset 08h[24]).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC1201UCL-266 | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA432 |
| SC1201UCL-266F | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA432 |
| SC12484CV-80 | PALETTE-DAC DSPL CTLR, PQCC44 |
| SC11483CV-110 | PALETTE-DAC DSPL CTLR, PQCC44 |
| SC11483CV-80 | PALETTE-DAC DSPL CTLR, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC1201UFH-266B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SC1201UFH-266F | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SC1201UFH-266FR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SC1202 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:600mA Low Dropout Positive Voltage Regulator |
| SC1202_04 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:600mA Low Dropout Positive Voltage Regulator |
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