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| 型號： | SB80L186EB8 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 8 MHz, MICROPROCESSOR, PQFP80 |
| 封裝： | SHRINK, QFP-80 |
| 文件頁數(shù)： | 3/59頁 |
| 文件大小： | 664K |
| 代理商： | SB80L186EB8 |
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80C186EB80C188EB 80L186EB80L188EB
Table 3 Pin Descriptions
(Continued)
Pin
Input
Output
Description
Name
Type
States
A1816
IO
A(L)
H(Z)
These pins provide multiplexed Address during the address
phase of the bus cycle Address bits 16 through 19 are presented
A19ONCE
R(WH)
on these pins and can be latched using ALE These pins are
(A15A8)
P(X)
driven to a logic 0 during the data phase of the bus cycle On the
(A1816)
80C188EB A15 – A8 provide valid address information for the
(A19ONCE)
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A1816 must not be driven
low during reset or improper operation may result
S20
O
H(Z)
Bus cycle Status are encoded on these pins to provide bus
transaction information S20 are encoded as follows
R(Z)
P(1)
S2
S1
S0
Bus Cycle Initiated
0
Interrupt Acknowledge
0
1
Read IO
0
1
0
Write IO
0
1
Processor HALT
1
0
Queue Instruction Fetch
1
0
1
Read Memory
1
0
Write Memory
1
Passive (no bus activity)
ALE
O
H(0)
Address Latch Enable
output is used to strobe address
information into a transparent type latch during the address phase
R(0)
of the bus cycle
P(0)
BHE
O
H(Z)
Byte High Enable
output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
(RFSH)
R(Z)
A0 have the following logical encoding
P(X)
A0
BHE
Encoding
(for the 80C186EB80L186EB only)
0
Word Transfer
0
1
Even Byte Transfer
1
0
Odd Byte Transfer
1
Refresh Operation
On the 80C188EB80L188EB RFSH is asserted low to indicate a
refresh bus cycle
RD
O
H(Z)
ReaD
output signals that the accessed memory or IO device
must drive data information onto the data bus
R(Z)
P(1)
WR
O
H(Z)
WRite
output signals that data available on the data bus are to be
written into the accessed memory or IO device
R(Z)
P(1)
READY
I
A(L)
READY
input to signal the completion of a bus cycle READY
must be active to terminate any bus cycle unless it is ignored by
S(L)
correctly programming the Chip-Select Unit
DEN
O
H(Z)
Data ENable
output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when data is
R(Z)
to be transferred on the bus
P(1)
NOTE
Pin names in parentheses apply to the 80C188EB80L188EB
11
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相關(guān)代理商/技術(shù)參數(shù) |
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| SB80L186EC13 | 功能描述:IC MPU 16-BIT 3V 13MHZ 100-SQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| SB80L186EC-13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| SB80L186EC16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| SB80L186EC20 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| SB80L186EC25 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
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