參數(shù)資料
型號(hào): SAX-XC878-16FFA3V3
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP64
封裝: PLASTIC, TQFP-64
文件頁數(shù): 8/139頁
文件大?。?/td> 4777K
代理商: SAX-XC878-16FFA3V3
XC878CLM
Functional Description
Advance Information
Data Sheet
98
V0.1, 2008-04
3.21
Controller Area Network (MultiCAN)
The MultiCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN
node can receive and transmit standard frames with 11-bit identifiers as well as extended
frames with 29-bit identifiers.
Both CAN nodes share a common set of message objects, where each message object
may be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects may be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double chained lists, where each CAN node has
it’s own list of message objects. A CAN node stores frames only into message objects
that are allocated to the list of the CAN node. It only transmits messages from objects of
this list. A powerful, command driven list controller performs all list operations.
The bit timings for the CAN nodes are derived from the peripheral clock (
f
CAN) and are
programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects
each CAN node to a bus transceiver.
Figure 29
Overview of the MultiCAN
Features
Compliant to ISO 11898.
MultiCANModule Kernel
MultiCAN_XC8_overview
Port
Control
CAN
Node 0
CANControl
Message
Object
Buffer
32
Objects
CAN
Node 1
TXDC0
RXDC0
TXDC1
RXDC1
Linked
List
Control
f
CAN
Clock
Control
Address
Decoder &
Data
control
AccessMediator
Interrupt
Controller
CANSRC[7:0]
A[13: 2]
D[31:0]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAX-XC878-16FFA5V 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit Single-Chip Microcontroller
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