參數(shù)資料
型號: SAX-XC878-16FFA3V3
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP64
封裝: PLASTIC, TQFP-64
文件頁數(shù): 115/139頁
文件大?。?/td> 4777K
代理商: SAX-XC878-16FFA3V3
XC878CLM
Functional Description
Advance Information
Data Sheet
70
V0.1, 2008-04
3.7
Reset Control
The XC878 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC878 is first powered up, the status of certain pins (see Table 24) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
The second type of reset in XC878 is the hardware reset. This reset function can be used
during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
3.7.1
Module Reset Behavior
Table 23 lists the functions of the XC878 and the various reset types that affect these
functions. The symbol “■” signifies that the particular function is reset to its default state.
Table 23
Effect of Reset on Device Functions
Module/
Function
Wake-Up
Reset
Watchdog
Reset
Hardware
Reset
Power-On
Reset
Brownout
Reset
CPU Core
■■■■■
Peripherals
■■■■■
On-Chip
Static RAM
Not affected,
Reliable
Not affected,
Reliable
Not affected,
Reliable
Affected, un-
reliable
Affected, un-
reliable
Oscillator,
PLL
Not affected ■■■
Port Pins
■■■■■
EVR
The voltage
regulator is
switched on
Not affected Not affected ■■
FLASH
■■■■■
NMI
Disabled
■■■
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