參數(shù)資料
型號: SAL-XC886C-8FFA5V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數(shù): 127/134頁
文件大?。?/td> 864K
代理商: SAL-XC886C-8FFA5V
SAL-XC886CLM
Functional Description
Data Sheet
85
V1.0, 2010-05
3.13.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
(3.7)
3.14
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 29). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock f
MOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
(3.8)
Table 30
Deviation Error for UART with Fractional Divider enabled
f
PCLK
Prescaling Factor
(BRPRE)
Reload Value
(BR_VALUE + 1)
STEP
Deviation
Error
20 MHz
1
10 (A
H)
230 (E6
H)
+0.03 %
10 MHz
1
5 (5
H)
230 (E6
H)
+0.03 %
6.67 MHz
1
3 (3
H)
212 (D4
H)
-0.16 %
5MHz
1
2 (2
H)
189 (BD
H)
+0.14 %
Mode 1, 3 baud rate
2
SMOD
f
PCLK
×
32
2
256
TH1
()
×
-----------------------------------------------------
=
f
MOD
f
DIV
1
256
STEP
------------------------------
×
=
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