參數(shù)資料
型號: SAK-XC2785X-72F80L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 21/141頁
文件大?。?/td> 1793K
代理商: SAK-XC2785X-72F80L
XC2785X
XC2000 Family / Base Line
Electrical Parameters
Data Sheet
117
V2.1, 2011-07
Note: The term CLKOUT refers to the reference clock output signal which is generated
by selecting
f
SYS as the source signal for the clock output signal EXTCLK on pin
P2.8 and by enabling the high-speed clock driver on this pin.
Variable Memory Cycles
External bus cycles of the XC2785X are executed in five consecutive cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module
using the READY handshake input.
This table provides a summary of the phases and the ranges for their length.
Note: The bandwidth of a parameter (from minimum to maximum value) covers the
whole operating range (temperature, voltage) as well as process variations. Within
a given device, however, this bandwidth is smaller than the specified range. This
is also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Note: Operating Conditions apply;
C
L =20pF.
Table 29
Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter
Valid Values Unit
Address setup phase, the standard duration of this
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
tpAB
1 … 2 (5)
TCS
Command delay phase
tpC
0 … 3
TCS
Write Data setup/MUX Tristate phase
tpD
0 … 1
TCS
Access phase
tpE
1 … 32
TCS
Address/Write Data hold phase
tpF
0 … 3
TCS
相關(guān)PDF資料
PDF描述
SAK-XC2785X-104F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
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