參數(shù)資料
型號: SAK-XC2785X-104F80L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 20/141頁
文件大?。?/td> 1793K
代理商: SAK-XC2785X-104F80L
XC2785X
XC2000 Family / Base Line
Electrical Parameters
Data Sheet
116
V2.1, 2011-07
4.6.5
External Bus Timing
The following parameters specify the behavior of the XC2785X bus interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Bus Interface Performance Limits
The output frequency at the bus interface pins is limited by the performance of the output
drivers. The fast clock driver (used for CLKOUT) can drive 80-MHz signals, the standard
drivers can drive 40-MHz signals
Therefore, the speed of the EBC must be limited, either by limiting the system frequency
to
f
SYS ≤ 80 MHz or by adding waitstates so that signal transitions have a minimum
distance of 12.5 ns.
For a description of the bus protocol and the programming of its variable timing
parameters, please refer to the User’s Manual.
Figure 22
CLKOUT Signal Timing
Table 28
EBC Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
CLKOUT Cycle Time
1)
1) The CLKOUT cycle time is influenced by PLL jitter. For longer periods the relative deviation decreases (see
PLL deviation formula).
t
5 CC
1 /
f
SYS
ns
CLKOUT high time
t
6 CC
2
CLKOUT low time
t
7 CC
2
CLKOUT rise time
t
8 CC
3ns
CLKOUT fall time
t
9 CC
3
MC_X_EBCCLKOUT
CLKOUT
t5
t6
t7
t8
t9
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