參數(shù)資料
型號: SAK-XC2768X-136F128L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 128 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù): 78/131頁
文件大小: 1711K
代理商: SAK-XC2768X-136F128L
XC2768X
XC2000 Family Derivatives / Premium Line
Functional Description
Preliminary
Data Sheet
50
V1.0, 2010-12
3.4
Instruction Cache (ICache)
The XC2768X contains 16 Kbytes of Instruction Cache (ICache). The ICache is a two-
way set-associative cache and is organized as 512 cache lines, with 128 bits per line.
Each ICache line has a single associated valid bit. A dedicated address space (see
Table 8) is reserved in which the program execution can be accelerated with enabled
ICache.
3.5
Memory Protection Unit (MPU)
The XC2768X’s Memory Protection Unit (MPU) protects user-specified memory areas
from unauthorized read, write, or instruction fetch accesses. The MPU can protect the
whole address space including the peripheral area. This completes established
mechanisms such as the register security mechanism or stack overrun/underrun
detection.
Four Protection Levels support flexible system programming where operating system,
low level drivers, and applications run on separate levels. Each protection level permits
different access restrictions for instructions and/or data.
Every access is checked (if the MPU is enabled) and an access violating the permission
rules will be marked as invalid and leads to a protection trap.
A set of protection registers for each protection level specifies the address ranges and
the access permissions. Applications requiring more than 4 protection levels can
dynamically re-program the protection registers.
3.6
Memory Checker Module (MCHK)
The XC2768X’s Memory Checker Module calculates a checksum (fractional polynomial
division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on
a 32-bit linear feedback shift register and may, therefore, also be used to generate
pseudo-random numbers.
The Memory Checker Module is a 16-bit parallel input signature compression circuitry
which enables error detection within a block of data stored in memory, registers, or
communicated e.g. via serial communication lines. It reduces the probability of error
masking due to repeated error patterns by calculating the signature of blocks of data.
The polynomial used for operation is configurable, so most of the commonly used
polynomials may be used. Also, the block size for generating a CRC result is
configurable via a local counter. An interrupt may be generated if testing the current data
block reveals an error.
An autonomous CRC compare circuitry is included to enable redundant error detection,
e.g. to enable higher safety integrity levels.
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