參數(shù)資料
型號： SAK-XC2768X-136F128L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 128 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 70/131頁
文件大?。?/td> 1711K
代理商： SAK-XC2768X-136F128L
XC2768X
XC2000 Family Derivatives / Premium Line
Functional Description
Preliminary
Data Sheet
43
V1.0, 2010-12
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
USIC0–3 alternate regs. 20’B000
H
20’BFFF
H
4 Kbytes
Accessed via EBC
MultiCAN alternate regs. 20’8000
H
20’AFFF
H
12 Kbytes
Accessed via EBC
Reserved
20’6000
H
20’7FFF
H
8 Kbytes
USIC0–3 registers
20’4000
H
20’5FFF
H
8 Kbytes
Accessed via EBC
Reserved
20’6800
H
20’7FFF
H
6 Kbytes
MultiCAN registers
20’0000
H
20’3FFF
H
16 Kbytes
Accessed via EBC
External memory area
01’0000
H
1F’FFFF
H
1984 Kbytes
SFR area
00’FE00
H
00’FFFF
H
0.5 Kbytes
Dualport RAM (DPRAM) 00’F600
H
00’FDFF
H
2 Kbytes
Reserved for DPRAM
00’F200
H
00’F5FF
H
1 Kbytes
ESFR area
00’F000
H
00’F1FF
H
0.5 Kbytes
XSFR area
00’E000
H
00’EFFF
H
4 Kbytes
Data SRAM (DSRAM)
00’8000
H
00’DFFF
H
24 Kbytes
External memory area
00’0000
H
00’7FFF
H
32 Kbytes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000
H to C0’FFFFH).
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Table 8
XC2768X Memory Map (cont’d)
1)
Address Area
Start Loc. End Loc.
Area Size
2)
Notes
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