參數(shù)資料
型號(hào): SAK-C164CH-8FM
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封裝: 0.65 MM PITCH, METRIC, PLASTIC, QFP-80
文件頁數(shù): 73/74頁
文件大?。?/td> 917K
代理商: SAK-C164CH-8FM
&
Data Sheet
6
1999-08
P4
P4.0
P4.1
P4.2
P4.3
P4.5
P4.6
17
18
19
22
23
24
IO
O
I
O
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 4 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:
1)
A16
Least Significant Segment Address Line,
CS3
Chip Select 3 Output
A17
Segment Address Line,
CS2
Chip Select 2 Output
A18
Segment Address Line,
CS1
Chip Select 1 Output
A19
Segment Address Line,
CS0
Chip Select 0 Output
A20
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A21
Most Significant Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output
RD
25
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL
26
O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.
ALE
27
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA
28
I
External Access Enable pin. A low level at this pin during and
after Reset forces the C164 to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
Table 2
Pin Definitions and Functions (continued)
Symbol Pin
Num.
Input
Outp.
Function
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