參數(shù)資料
型號: SAK-C164CH-8FM
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封裝: 0.65 MM PITCH, METRIC, PLASTIC, QFP-80
文件頁數(shù): 48/74頁
文件大?。?/td> 917K
代理商: SAK-C164CH-8FM
&
Data Sheet
50
1999-08
Direct Drive
When pins P0.15-13 (P0H.7-5) equal 011
B during reset the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
I
CPU directly follows the frequency of IOSC so the high and low time of
I
CPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
I
OSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCL
min = 1/IOSC * DCmin
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of
I
OSC is compensated
so the duration of 2TCL is always 1/
I
OSC. The minimum value TCLmin therefore has to be
used only once for timings that require an odd number of TCLs (1,3,...). Timings that
require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/
I
OSC.
Note: The address float timings in Multiplexed bus mode (
W
11 and W45) use the maximum
duration of TCL (TCL
max = 1/IOSC * DCmax) instead of TCLmin.
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