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C165UTAH
External Bus Interface
Data Sheet
184
2001-02-23
signals. This saves the external combination of the WR signal with A0 or BHE. In this
case pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high
byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and
BHE. The respective byte will be written on both data bus halfs.
When reading bytes from an external 16-bit device, whole words may be read and the
C165UTAH automatically selects the byte to be input and discards the other. However,
care must be taken when reading devices that change state when being read, like
FIFOs, interrupt status registers, etc. In this case individual bytes should be selected
using BHE and A0.
Note:
PORT1 gets available for general purpose I/O, when none of the BUSCON
registers selects a demultiplexed bus mode.
Disable/Enable Control for Pin BHE
(
BYTDIS)
Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The
function of the BHE pin is enabled, if the BYTDIS bit contains a '0'. Otherwise, it is
disabled and the pin can be used as standard I/O pin. The BHE pin is implicitly used by
the External Bus Controller to select one of two byte-organized memory chips, which are
connected to the C165UTAH via a word-wide external data bus. After reset the BHE
function is automatically enabled (BYTDIS = '0'), if a 16-bit data bus is selected during
reset, otherwise it is disabled (BYTDIS=’1’). It may be disabled, if byte access to 16-bit
memory is not required, and the BHE signal is not used.
Segment Address Generation
During external accesses the EBC generates a (programmable) number of address lines
on Port 4, which extend the 16-bit address output on PORT0 or PORT1, and so increase
the accessible address space. The number of segment address lines is selected during
reset and coded in bit field SALSEL in register RP0H (see table below).
Bus Mode
Transfer Rate (
Speed factor
for byte/word/dword access
)
System Requirements
Free I/O
Lines
8-bit Multiplexed
Very low
( 1.5 / 3 / 6 )
Low (8-bit latch, byte bus)
P1H, P1L
8-bit Demultipl.
Low
( 1 / 2 / 4 )
Very low (no latch, byte bus) P0H
16-bit Multiplexed
High
( 1.5 / 1.5 / 3 )
High (16-bit latch, word bus) P1H, P1L
16-bit Demultipl.
Very high
( 1 / 1 / 2 )
Low (no latch, word bus)
---
SALSEL
Segment Address Lines
Directly accessible Address Space
1 1
Two:
A17...A16
256
KByte (Default without pull-downs)
1 0
Seven:
A22...A16
8
MByte (Maximum)