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C165UTAH
Interrupt and Trap Functions
Data Sheet
103
2001-02-23
7.1
Interrupt System Structure
The C165UTAH provides up to 64 separate interrupt nodes that may be assigned to 16
priority levels. The 4 lowest nodes are reserved for the CPU - thus, up to 60 nodes are
available for all interrupts. In order to support modular and consistent software design
techniques, each source of an interrupt or PEC request is supplied with a separate
interrupt control register and interrupt vector. The control register contains the interrupt
request flag, the interrupt enable bit, and the interrupt priority of the associated source.
Each source request is activated by one specific event, depending on the selected
operating mode of the respective device. The only exceptions are the two serial channels
of the table, where an error interrupt request can be generated by different kinds of error,
and the two subnode interrupts controlled by the ISNC and CLISNC registers (see
Interrupt and PEC descriptions). However, specific status flags which identify the type of
error are implemented in the serial channels’ control registers.
The C165UTAH provides a vectored interrupt system. In this system specific vector
locations in the memory space are reserved for the reset, trap, and interrupt service
functions. Whenever a request occurs, the CPU branches to the location that is
associated with the respective interrupt source. This allows direct identification of the
source that caused the request. The only exceptions are the class B hardware traps,
which all share the same interrupt vector. The status flags in the Trap Flag Register
(TFR) can then be used to determine which exception caused the trap. For the special
software TRAP instruction, the vector address is specified by the operand field of the
instruction, which is a seven bit trap number.
The reserved vector locations build a jump table in the low end of the C165UTAH’s
address space (segment 0). The jump table is made up of the appropriate jump
instructions that transfer control to the interrupt or trap service routines, which may be
located anywhere within the address space. The entries of the jump table are located at
the lowest addresses in code segment 0 of the address space. Each entry occupies 2
words, except for the reset vector and the hardware trap vectors, which occupy 4 or 8
words.
The table below lists all sources that are capable of requesting interrupt or PEC service
in the C165UTAH, the associated interrupt vectors, their locations, their trap numbers
and the SFR addresses of associated interrupt control registers. It also lists the
mnemonics of the corresponding Interrupt Enable flags. The mnemonics are composed
of a part that specifies the respective source, followed by a part that specifies their
function (IE=Interrupt Enable flag). The same composition is used for the mnemonics of
according interrupt request flags (IR=Interrupt Request flag; example: CC0IR belongs to
interrupt source CC0INT) and for the names of according interrupt control registers
(IC=Interrupt Control; example: CC0IC) which are not included in
Table 23
.