參數(shù)資料
型號: SAF-XC2264-72F66L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP100
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù): 42/116頁
文件大小: 1516K
代理商: SAF-XC2264-72F66L
XC2267 / XC2264
XC2000 Family Derivatives
General Device Information
Data Sheet
29
V2.1, 2008-08
99
ESR0
O0 / I St/B
External Service Request 0
Note: After power-up, ESR0 operates as open-
drain bidirectional reset with a weak pull-up.
U1C0_DX0E
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX2B
I
St/B
USIC1 Channel 0 Shift Control Input
10
V
DDIM
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Table 12
for details.
38,
64,
88
V
DDI1
-
PS/1 Digital Core Supply Voltage for Domain 1
Decouple with a ceramic capacitor, see Table 12
for details.
All
V
DDI1 pins must be connected to each other.
14
V
DDPA
-
PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent
V
DDP/VSS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6, and
P15 are fed from supply voltage
V
DDPA.
2,
25,
27,
50,
52,
75,
77,
100
V
DDPB
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
V
DDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6, and P15 are fed from supply
voltage
V
DDPB.
1,
26,
51,
76
V
SS
-
PS/-- Digital Ground
All
V
SS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected to
V
SS.
The respective board area must be
connected to ground (if soldered) or left free.
1) To generate the reference clock output for bus timing measurement,
fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
Table 4
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
相關PDF資料
PDF描述
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