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參數(shù)資料
| 型號(hào)： | SAF-C161O-LM HA |
| 廠商： | Infineon Technologies |
| 文件頁(yè)數(shù)： | 35/66頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16BIT ROM/LESS MQFP-80-1 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | C16xx |
| 核心處理器： | C166 |
| 芯體尺寸： | 16-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 63 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 80-QFP |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | SAF-C161O-LMHACT SAF-C161O-LMHACT-ND SAF-C161O-LMHAINCT |
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C161K
C161O
Data Sheet
36
V2.0, 2001-01
AC Characteristics
Definition of Internal Timing
The internal operation of the C161K/O is controlled by the internal CPU clock
fCPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 8).
Figure 8
Generation Mechanisms for the CPU Clock
The CPU clock signal
fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
fCPU. This influence must
be regarded when calculating the timings for the C161K/O.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9 associates the combinations of these three bits with the respective clock
generation mode.
MCT04826
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
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