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SAB 82532/SAF 82532
ASYNC Mode
Detailed Register Description
Semiconductor Group
193
07.96
Interrupt Status Register 1 (ISR1)
Access: read
address: ch-A: 3B
H
ch-B: 7B
H
Value after RESET: 00
H
All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding
interrupt vector is output.
Note: If bit IPC:VIS is set ‘1’, interrupt statuses in ISR1 may be flagged although they are
masked via register IMR1. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
PLLA…
DPLL Asynchronous
This bit is only valid when the receive clock is supplied by the
DPLL and FM0, FM1 or Manchester data encoding is selected.
It is set when the DPLL has lost synchronization. Reception is
disabled (IDLE is inserted) until synchronization has been
regained. Additionally, transmission is also interrupted if the
transmit clock is derived from the DPLL.
Carrier Detect Status Change
Indicates that a state transition has occurred on CD. The actual
state of CD can be read from the VSTR register.
Receive FIFO Overflow
This interrupt is generated if RFIFO is full and a further character
is received. This interrupt can be used for statistical purposes and
indicates that the CPU does not respond quickly enough to an
RPF or TCD interrupt.
Receive Pool Full
This bit is set if RFIFO is filled with data (character and optional
status information) up to the programmed threshold level.
Note: This interrupt is only generated in Interrupt Mode.
CDSC …
RFO …
RPF …
7
0
ISR1
BRK
BRKT
ALLS
XOFF
TIN
CSC
XON
XPR