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SAB 82532/SAF 82532
Detailed Register Description
Semiconductor Group
120
07.96
Receive Status Register (RSTA)
Access: read
address: ch-A: 21
H
ch-B: 61
H
Note: The contents of the RSTA register relates to the last received HDLC frame and is
updated when end-of-frame is recognized at the serial receive interface.
Additionally, RSTA byte is copied into RFIFO (last byte of each stored frame).
Thus, after RME interrupt instead of the contents of RSTA register the RSTA byte
stored in the RFIFO as the last byte of each frame should be evaluated.
7
0
RSTA
VFR
RDO
CRC
RAB
HA1
HA0
C/R
LA
VFR
…
Valid Frame
Determines whether a valid frame has been received.
1 … valid
0 … invalid.
An invalid frame is either
a frame which is not an integer number of 8 bits (n
×
8 bits) in
length (e.g. 25 bits), or
a frame which is too short taking into account the operation
mode selected via MODE (MDS1, MDS0, ADM) and the
selected CRC algorithm (CCR2:C32) and the selection of
receive CRC ON/OFF (CCR3:RCRC) as follows:
– auto-/non-auto mode (16-bit address), RCRC = 0 :
4 bytes (CRC-CCITT) or 6 (CRC-32)
– auto-/non-auto mode (16-bit address), RCRC = 1 :
3-4 bytes (CRC-CCITT) or 3-6 (CRC-32)
– auto-/non-auto mode (8-bit address), RCRC = 0 :
3 bytes (CRC-CCITT) or 5 (CRC-32)
– auto-/non-auto-mode (8-bit address), RCRC = 1 :
2-3 bytes (CRC-CCITT) or 2-5 (CRC-32)
– transparent mode 1: 3 bytes (CRC-CCITT) or 5 (CRC-32)
– transparent mode 0: 2 bytes (CRC-CCITT) or 4 (CRC-32)
Note: Shorter frames are not reported.
Receive Data Overflow
A data overflow has occurred during reception of the frame.
Additionally, an interrupt can be generated (refer to
ISR1:RDO / IMR1:RDO).
RDO …
HDLC Mode