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SAB 82532/SAF 82532
Introduction
Semiconductor Group
13
07.96
28
63
RES
I
Reset
A high signal on this pin forces the ESCC2
into reset state. During Reset the ESCC2
is in power up mode, after Reset in
power-down mode. Re-activation of each
channel is done via bit CCR0:PU (refer to
chapter 9.2
).
During Reset
– all uni-directional output stages are in
high-impedance state,
– all bi-directional output stages (data
bus) are in high-impedance state,
– output XTAL2 is in high-impedance if
input XTAL1 is ‘high’ (the internal
oscillator is disabled during reset),
– signals RD and INTA have to be ‘high’
10
42
BHE/
BLE
I
Bus High Enable
(Siemens/Intel bus mode)
If 16-bit bus interface mode is enabled,
this signal indicates a data transfer on the
upper byte of the data bus (D8…D15). In
8-bit bus interface mode this signal has no
function and should be tied to
V
DD
. Refer
to
chapter 3.1
for detailed information.
Bus Low Enable
(Motorola bus mode)
If 16-bit bus interface mode is enabled,
this signal indicates a data transfer on the
lower byte of the data bus (D0 … D7). In
8-bit bus interface mode this signal has no
function and should be tied to
V
DD
. Refer
to
chapter 3.1
for detailed information.
29
64
WIDTH
I
Width Of Bus Interface
(Bus Interface Mode)
A low signal on this input selects the 8-bit
bus interface mode. A high signal on this
input selects the 16-bit bus interface
mode. In this case word transfer to/from
the internal registers is enabled.
Moreover, byte transfers (in conjunction
with A0 and BHE/BLE) are allowed, too.
1.3
Pin Definitions and Functions
(cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Function
P-LCC-68
P-MQFP-80