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參數(shù)資料
| 型號(hào)： | SAB-XC164SM-8F40F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 8/66頁(yè) |
| 文件大?。?/td> | 613K |
| 代理商： | SAB-XC164SM-8F40F |
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XC164SM
Derivatives
Functional Description
Data Sheet
14
V1.0, 2005-11
3
Functional Description
The architecture of the XC164SM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164SM.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164SM.
Figure 3-1
Block Diagram
Interrupt Bus
XTAL
Osc / PLL
C lock Genera tio n
RTC
WDT
GPT
T2
T3
T4
T5
T6
SSC0
BRGen
(SPI)
ASC1
BRGen
(USART)
ADC
8/10-Bit
14
Channels
CC2
T7
T8
ProgMem
14
Port 5
PSRAM
2 K by tes
DPRAM
2 K bytes
DSRAM
2 K bytes
(8 F device)
C 1 6 6 SV2 -C ore
PM
U
DMU
CPU
ASC0
BRGen
(USART)
SSC1
BRGen
(SPI)
PORT1
Port 3
Port 9
14
13
6
Interrupt & PEC
Peripheral Data Bus
OCDS
D ebug Su p port
CC6
T12
T13
6 4 K by tes (8 F de vice)
3 2 K bytes (4 F de vice)
mc_xc164sm_block.vsd
Flash
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