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| 型號： | SAB-XC164SM-8F40F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 59/66頁 |
| 文件大小： | 613K |
| 代理商： | SAB-XC164SM-8F40F |
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XC164SM
Derivatives
Electrical Parameters
Data Sheet
60
V1.0, 2005-11
4.4.2
On-chip Flash Operation
The XC164SM’s Flash module delivers data within a fixed access time (see Table 4-9).
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
t
ACC of the Flash array. The required Flash waitstates depend on the actual system
frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash
accesses must be executed with 1 waitstate: ((1+1)
× 25 ns) ≥ 50 ns.
indicates the interrelation of waitstates and system frequency.
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for XC164SM-xF20F devices).
Table 4-9
Flash Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
Min.
Typ.
Max.
Flash module access time
t
ACC
CC ––50
1)
1) The actual access time is influenced by the system frequency, see Table 4-10.
ns
Programming time per 128-byte block
t
PR
CC –
2
2)
2) Programming and erase time depends on the system frequency. Typical values are valid for 40MHz.
5ms
Erase time per sector
t
ER
CC –
200
500
ms
Table 4-10
Flash Access Waitstates
Required Waitstates
Frequency Range
0 WS (WSFLASH = 00
B)
f
CPU ≤ 20 MHz
1 WS (WSFLASH = 01
B)
f
CPU ≤ 40 MHz
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