參數(shù)資料
型號(hào): SAA8122A
廠商: NXP Semiconductors N.V.
英文描述: Digital Still Camera Processor (ImagIC family)(數(shù)字靜態(tài)照相處理器)
中文描述: 數(shù)碼相機(jī)處理器(夢(mèng)想家家庭)(數(shù)字靜態(tài)照相處理器)
文件頁(yè)數(shù): 12/26頁(yè)
文件大?。?/td> 885K
代理商: SAA8122A
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
Objective specification
Rev. 01 — 20 April 2000
12 of 26
9397 750 07048
Philips Electronics N.V. 2000. All rights reserved.
SD_D[4]
SD_RAS
SD_D[6]
SD_D[13]
IO30
IO37
A24
A19
A18
A13
A5
CS6
CAS1
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
SDRAM controller data bus bit 4
SDRAM controller row address strobe; active LOW
SDRAM controller data bus bit 6
SDRAM controller data bus bit 13
I/O port 3 bit 6
I/O port 4 bit 5
EBIU A24 (Strapin[1] during boot sequence)
EBIU A19 (Strapin[6] and Strapin[9] during boot sequence)
EBIU A18 (Strapin[10] during boot sequence)
EBIU A13
EBIU A5
EBIU controller chip select 6; active LOW
EBIU controller CAS signal for DRAM memory for upper byte; used as data
strobe signal for upper byte for general chip select; active LOW
EBIU controller output enable signal; active LOW
EBIU controller RAS signal for DRAM memory; active LOW
SDRAM controller column address strobe; active LOW
SDRAM controller write enable; active LOW
SDRAM controller data bus bit 3
SDRAM controller data bus bit 8
SDRAM controller data bus bit 10
SDRAM controller data bus bit 14
I/O port 3 bit 2
I/O port 3 bit 5
I/O port 4 bit 1
I/O port 4 bit 4
EBIU A23 (Strapin[2] during boot sequence)
EBIU A16
EBIU A12
EBIU A3
EBIU controller chip select 7; active LOW
EBIU controller chip select 4; active LOW
EBIU controller write enable signal; active LOW
EBIU controller wait signal for chip selects; active LOW
SDRAM controller DQ mask enable for byte 0; active LOW
SDRAM controller DQ mask enable for byte 1; active LOW
SDRAM controller data bus bit 2
SDRAM controller data bus bit 9
SDRAM controller data bus bit 11
SDRAM controller data bus bit 15
I/O port 3 bit 3
OE
RAS
SD_CAS
SD_WE
SD_D[3]
SD_D[8]
SD_D[10]
SD_D[14]
IO26
IO29
IO33
IO36
A23
A16
A12
A3
CS7
CS4
WE
CS_WAIT
SD_DQM0
SD_DQM1
SD_D[2]
SD_D[9]
SD_D[11]
SD_D[15]
IO27
R17
R18
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
U2
U3
U4
U5
U6
U7
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
Table 3:
Symbol
Pin description
…continued
Pin
Type
Description
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