
Philips Semiconductors
SAA8122A
Digital Still Camera Processor (ImagIC family)
Objective specification
Rev. 01 — 20 April 2000
11 of 26
9397 750 07048
Philips Electronics N.V. 2000. All rights reserved.
SC_CLE
SD_A[12]
SD_A[13]
SD_A[14]
SD_A[10]
SD_A[6]
SD_A[5]
V
DD
V
DD
V
DD
V
DD
V
DD
SC_ALE
PC2_CE1
PC2_CE2
PC_REG
PC_WAIT1
IOWR_WE
IORD_RE
SD_CLKOUT
SD_CLKIN
SD_CS2
SD_CLKEN
SD_A[11]
V
DD
SD_D[7]
IO25
IO38
A25
A21
V
DD
A14
SCLK
A9
CAS0
M18
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
O
O
O
O
O
O
O
-
-
-
-
-
O
O
O
O
O
O
O
O
I
O
O
O
-
I/O
I/O
I/O
I/O
I/O
-
I/O
O
I/O
O
EBIU controller CLE signal for SSFDC card
SDRAM controller address bus bit 12
SDRAM controller address bus bit 13
SDRAM controller address bus bit 14
SDRAM controller address bus bit 10
SDRAM controller address bus bit 6
SDRAM controller address bus bit 5
supply voltage
supply voltage
supply voltage
supply voltage
supply voltage
EBIU controller ALE signal for SSFDC card
EBIU controller CE1 signal for PC card 2; active LOW
EBIU controller CE2 signal for PC card 2; active LOW
EBIU controller REG signal for PC cards; active LOW
EBIU controller WAIT signal for PC card 1; active LOW
EBIU controller IORD signal for PC cards; active LOW
EBIU controller IORD signal for PC cards; active LOW
SDRAM controller clock output
SDRAM controller clock input
SDRAM controller chip select for memory 2; active LOW
SDRAM controller clock enable
SDRAM controller address bus bit 11
supply voltage
SDRAM controller data bus bit 7
I/O port 3 bit 1
I/O port 4 bit 6
EBIU A25 (Strapin[0] during boot sequence)
EBIU A21 (Strapin[4] during boot sequence)
supply voltage
EBIU A14
EBIU controller clock signal for external peripherals
EBIU A9
EBIU controller CAS signal for DRAM memory for lower byte; used as data
strobe signal for lower byte for general chip select; active LOW
EBIU controller CE1 signal for PC card 1; active LOW
EBIU controller CE2 signal for PC card 1; active LOW
SDRAM controller chip select for memory 0; active LOW
SDRAM controller chip select for memory 1; active LOW
SDRAM controller chip select for memory 3; active LOW
PC1_CE1
PC1_CE2
SD_CS0
SD_CS1
SD_CS3
P17
P18
R1
R2
R3
O
O
O
O
O
Table 3:
Symbol
Pin description
…continued
Pin
Type
Description