參數(shù)資料
型號(hào): SAA7382
廠商: NXP Semiconductors N.V.
英文描述: Error correction and host interface IC for CD-ROM ELM
中文描述: 錯(cuò)誤更正和主機(jī)接口集成電路的CD - ROM榆木
文件頁(yè)數(shù): 5/60頁(yè)
文件大?。?/td> 226K
代理商: SAA7382
1996 Apr 25
5
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7382
6
PINNING
SYMBOL
PIN
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
I
I
O
I
I
I
I
I
I/O
I
O
I
I
DESCRIPTION
DGND1
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15/RAS
RA16/CAS
RWE
DGND2
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
TEST2
DGND3
TEST1
CROUT
CRIN
SFSY
RCK
SUB
BCK
V
DDD1
WS
DATA
C2PO
SDA
SCL
INT
RESET
SYN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
digital ground 1
buffer RAM address bus output line 6
buffer RAM address bus output line 7
buffer RAM address bus output line 8
buffer RAM address bus output line 9
buffer RAM address bus output line 10
buffer RAM address bus output line 11 (SRAM) only
buffer RAM address bus output line 12 (SRAM) only
buffer RAM address bus output line 13 (SRAM) only
buffer RAM address bus output line 14 (SRAM) only
buffer RAM address bus output line 15 (SRAM) or RAS (DRAM)
buffer RAM address bus output line 16 (SRAM) or CAS (DRAM)
buffer RAM write enable output
digital ground 2
buffer RAM data bus bidirectional line 0
buffer RAM data bus bidirectional line 1
buffer RAM data bus bidirectional line 2
buffer RAM data bus bidirectional line 3
buffer RAM data bus bidirectional line 4
buffer RAM data bus bidirectional line 5
buffer RAM data bus bidirectional line 6
buffer RAM data bus bidirectional line 7
test input 2
digital ground 3
test input 1
clock oscillator output
clock oscillator input
serial subcode input frame sync input
serial subcode clock output (active LOW)
serial input for Q-to-W subcode input
serial interface bit clock input
digital supply voltage 1 (3.3 V)
serial interface word clock input
serial data input
serial interface flag input
sub-CPU serial data input/output
sub-CPU serial clock input
sub-CPU open-collector interrupt output
power-on reset input (active LOW)
sync signal input from sub-CPU
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