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參數(shù)資料
| 型號： | SAA7382 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Error correction and host interface IC for CD-ROM ELM |
| 中文描述： | 錯誤更正和主機(jī)接口集成電路的CD - ROM榆木 |
| 文件頁數(shù)： | 15/60頁 |
| 文件大?。?/td> | 226K |
| 代理商： | SAA7382 |
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1996 Apr 25
15
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7382
Bit 7 of the DACHH register specifies which memory is
accessed. If the bit is clear then the address refers to the
external memory, if the bit is set then the address refers to
the 4 kbyte internal memory. The internal memory should
not be accessed during error correction.
This register should be written to before each data transfer
because its value will be undefined at the end of the
previous transfer.
7.7.7
PTL, PTH
AND
PTHH
This register holds a 21-bit pointer to the external buffer
memory address of the head of the current data block after
correction.
The SAA7382 defines the minute byte in the header to be
at the head of the block, and the 12 sync bytes at the tail
of the block. Each block contained in the buffer is taken to
be 2352 bytes.
The controller can transfer the decoded block back to the
host by copying the address of this register to the DACL,
DACH and DACHH pointers after a decoder interrupt.
When the WRRQ bit in the CTRL0 register is set to logic 1,
this pointer is updated at the sync signal of every
2352 byte clocks.
7.7.8
WAL, WAH
AND
WAHH
These registers contain a 21-bit address of where raw data
from the drive is written to the external buffer memory. The
pointer is automatically incremented during data transfer.
The pointer should only be read while drive data writes to
the buffer are disabled. If WAHH is written to while drive
data write is enabled, then the new WA value will be used
for the first byte of the next sector. The new pointer value
is temporarily stored in the PT register. This cannot be
read after WA has been written to.
7.7.9
DTRG
Writing to this register starts a data transfer. The data
written is discarded.
7.7.10
DTACK
Writing to this register clears the DTEI interrupt. The data
written is discarded.
7.7.11
HEAD0, HEAD1, HEAD2
AND
HEAD3
These registers are used to hold the header and the
sub-header data of the current block.
To read the header data set, the SHDREN bit in the
CTRL1 register is set to logic 0; to read the sub-header
data, SHDREN is set to logic 1.
If sub-header is selected, the registers will normally hold
data from bytes 20 to 23. However, if the error flag for one
of these bytes is set, then the byte is taken from the first
sub-header field. (bytes 16 to 19.)
The error flags for header and sub-header can be read
from the STAT1 register. No error correction is performed
on header or sub-header.
Header and sub-header registers are valid directly after
decoder interrupt, and as long as the VALST bit in the
STAT3 register is LOW. In all write modes they contain
information on the block whose header is pointed to by
PTL, PTH and PTHH.
Table 5
HEAD registers
SHDREN
REGISTER
CONTENTS
0
0
0
0
1
1
1
1
HEAD0
HEAD1
HEAD2
HEAD3
HEAD0
HEAD1
HEAD2
HEAD3
MINUTES (byte 12)
SECONDS (byte 13)
FRAMES (byte 14)
MODE (byte 15)
FILE NUMBER (byte 16 or 20)
CHANNEL NUMBER (byte 17 or 21)
SUBMODE NUMBER (byte 18 or 22)
CODING INFORMATION (byte 19 or 23)
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