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參數(shù)資料
| 型號： | SAA7382 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Error correction and host interface IC for CD-ROM ELM |
| 中文描述： | 錯誤更正和主機接口集成電路的CD - ROM榆木 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 226K |
| 代理商： | SAA7382 |
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1996 Apr 25
17
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7382
Table 7
Error correction modes
Note
1.
Where X = don’t care.
7.7.13
CTRL1
The reset function clears all the flags in this register.
Table 8
CTRL1 register bits
DECEN
lookahead
WRRQ
ECCRQ
decoder mode
0
1
1
1
1
1
1
X
0
0
0
0
1
1
X
0
0
1
1
1
1
X
0
1
0
1
0
1
decoder disable; note 1
monitor only
repeat correction
write only
real-time correct, normal mode
write only, lookahead
real-time correct, lookahead
BIT
NAME
FUNCTION
7
SYIEN
Disable sync interpolation = 0; Enable sync interpolation = 1. Enabling SYIEN prevents
loss of synchronization when an error occurs in a sync pattern during data read.
Disable sync detection = 0; Enable sync detection = 1. Enabling SYDEN synchronizes
the decoder with the sync pattern detected in the input data.
Descramble disable (audio) = 0; Descramble enable = 1. This bit enables/disables
descrambling. Setting this bit to logic 0 allows reading of raw data on disc, even audio
signals. This bit should be set to logic 1 for CROM data.
CRC with error correction disabled = 0; Detection errors are corrected = 1. This bit
enables/disables rewriting of error bytes in the buffer during error correction. Setting
the bit to logic 0 allows CRC checks without error correction.
Mode 1 request = 0; Mode 2 request = 1. This bit discriminates Mode 1/Mode 2.
Form 1 request = 0; Form 2 request = 1. This bit discriminates Mode 2/Form 1 and
Mode 2/Form 2.
Disable mode check function = 0; Enable mode check function = 1. If the mode
specified in the mode byte does not correspond with the raw data mode bit and this bit
is set to logic 1 then error correction and detection is disabled.
Header data on registers Head0 to Head3 = 0; Sub-header data on registers
Head0 to Head3 = 1. This bit toggles header and sub-header data between registers
HEAD0 to HEAD3.
6
SYDEN
5
DSCREN
4
COWREN
3
2
MODRQ
FORMRQ
1
MBCKRQ
0
SHDREN
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