參數(shù)資料
型號(hào): SAA7380
廠商: NXP Semiconductors N.V.
英文描述: Error correction and host interface IC for CD-ROM ELM
中文描述: 錯(cuò)誤更正和主機(jī)接口集成電路的CD - ROM榆木
文件頁(yè)數(shù): 42/60頁(yè)
文件大?。?/td> 227K
代理商: SAA7380
1996 Apr 25
42
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7380
Notes
1.
2.
3.
4.
All timings are for single-speed, they should be divided by the speed up to eight times speed.
T represents half a clock period.
The timings for this mode can only be met with a 33 MHz clock.
CLK = 1 clock period.
t
7
HWR/HRD inactive
33 MHz clock
16 MHz clock
60
145
50
20
5
3CLK
80
60
ns
ns
ns
ns
ns
ns
ns
t
8
t
9
t
10
t
11
t
12
8-
BIT
DMA
DATA TRANSFER
; see Fig.23
HWR data set-up
HWR data hold
HRD data access
HRD data to 3-state
cycle time
t
0
t
1
t
2
t
3
t
4
DMARQ to DMACK
HWR/HRD to DMARQ inactive
DMACK set-up
DMACK hold
HWR/HRD active
0
30
0
50
75
60
145
50
20
80
80
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33 MHz clock
16 MHz clock
33 MHz clock
16 MHz clock
t
5
HWR/HRD inactive
t
6
t
7
t
8
t
9
P
SEUDO
16-
BIT
DMA
READ TRANSFER
; see Fig.24; note 4
HWR data set-up
HWR data hold
HRD data access
HRD data to 3-state
t
0
t
1
t
2
t
3
HRD to DMARQ inactive
DMARQ to DMACK
HRD inactive to DMACK inactive
HRD active
0
0
50
65
CLK
2CLK
2CLK
80
CLK
80
60
5CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33 MHz clock
16 MHz clock
t
4
t
5
t
6
t
7
t
8
t
9
t
10
HFBC to data valid
data 3-state to HFBC inactive
HRD data access
HRD data to 3-state
HFBC active
data valid to HFBLB
HFBLB to HFBC inactive
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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