參數(shù)資料
型號(hào)： SAA7380
廠商： NXP Semiconductors N.V.
英文描述： Error correction and host interface IC for CD-ROM ELM
中文描述： 錯(cuò)誤更正和主機(jī)接口集成電路的CD - ROM榆木
文件頁(yè)數(shù)： 28/60頁(yè)
文件大小： 227K
代理商： SAA7380
1996 Apr 25
28
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7380
7.9.2.3
HCON
Table 28
HCON register bits
Note
1.
Where X = don’t care.
This is the host configuration register. Resetting SAA7380 clears this register.
BIT 7
(1)
BIT 6
(1)
BIT 5
(1)
BIT 4
(1)
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
X
DTS
SDRQ
LOHI
DMA16
Bit DTS is the suspend transfer bit. Setting this bit HIGH
suspends non-DMA transfers and allows the host to
access the COMIN and SBOUT registers. During DMA
transfers this bit has no effect.
If SDRQ is LOW and the SELRQ pin is LOW then DMA
transfer is selected otherwise non-DMA transfer is
selected.
The pseudo 16-bit DMA read transfer is selected by setting
bit DMA16 HIGH. DMA transfer must also be selected for
this mode to operate. host writes are always 8-bit and are
not affected by this bit.
The LOHI bit when HIGH causes the pseudo 16-bit DMA
transfer to be a LOW byte followed by a HIGH byte. Setting
it LOW causes the sequence to be a HIGH byte followed
by a LOW byte. If the 16-bit DMA mode is not selected
then this bit has no effect.
7.9.3
ATAPI M
ODE
The following registers are accessible by the ATAPI host.
Most of these registers are identical to the sub-CPU
registers with the same name.
Table 29
ATAPI registers
ADDRESS
WRITE HWR
READ HRD
WIDTH
CS2
CS1
DA2
DA1
DA0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
DATA
AFEAT
AINTR
ASAMT
DBCL
DBCH
ADRSEL
ACMD
ADCTR
reserved
DATA
AERR
AINTR
ASAMT
DBCL
DBCH
ADRSEL
ASTAT
Alt Status
ADRADR
16
8
8
8
8
8
8
8
8
8
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