參數資料
型號: SAA7325H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Digital servo processor and Compact Disc decoder with integrated DAC CD10
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: PLASTIC, SOT-393-1, QFP-64
文件頁數: 55/68頁
文件大?。?/td> 273K
代理商: SAA7325H
1999 Jun 17
55
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10)
SAA7325
11 OPERATING CHARACTERISTICS (I
2
S-BUS TIMING)
V
DD
= 3.0 to 3.6 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
Note
1.
In lock-to-disk mode, the I
2
S-bus timing is directly related to the disc speed factor ‘d’. In normal operation, d = 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
2
S-bus timing (d = 1 for normal operation);
see Fig.33; note 1
C
LOCK OUTPUT
:
PIN
SCLK (C
L
= 20 pF)
T
cy
output clock period
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
166/d
83/d
42/d
166/d
83/d
42/d
472.4/d
236.2/d
118.1/d
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CH
clock HIGH time
t
CL
clock LOW time
O
UTPUTS
:
PINS
WCLK, DATA
AND
EF (C
L
= 20 pF)
t
su
set-up time
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
95/d
48/d
24/d
95/d
48/d
24/d
ns
ns
ns
ns
ns
ns
t
h
hold time
Fig.33 I
2
S-bus timing diagram.
VDD
0.8 V
VDD
0.8 V
tCH
MBG407
tCL
clock period Tcy
SCLK
WCLK
DATA
EF
th
tsu
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