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參數(shù)資料
| 型號(hào)： | SAA2013 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 中文描述： | 自適應(yīng)分配和戴納信貸混凝劑縮放系統(tǒng)編碼 |
| 文件頁數(shù)： | 25/32頁 |
| 文件大?。?/td> | 137K |
| 代理商： | SAA2013 |
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May 1994
25
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
Notes
1.
2.
T
c256
is a clock period of FS256.
T
c24
is a clock period of CLK24.
D
ATA MODE
;
SEE
F
IG
.15
t
d1
L3MODEC HIGH to L3CLKC
LOW
L3CLKC HIGH time
L3CLKC LOW time
L3DATAC input set-up time
before L3CLKC HIGH
L3DATAC input hold time after
L3CLKC HIGH
L3CLKC HIGH time before
L3MODEC LOW
L3MODEC HIGH to L3DATAC
output valid
L3DATAC output hold time
after L3CLKC HIGH
L3CLKC HIGH to L3DATAC
output valid
190
ns
t
cH
t
cL
t
su1
210
210
100
ns
ns
ns
t
h1
30
ns
t
h2
190
ns
t
d3
380
ns
t
h3
120
ns
t
d4
360
530
ns
ns
between bits 7
and 8; no halt
mode used
H
ALT MODE
;
SEE
F
IG
.18
t
L
t
d1
L3MODEC LOW time
L3MODEC HIGH to L3CLKC
HIGH delay time
L3CLKC HIGH time before
L3MODEC LOW
190
190
ns
ns
t
h2
190
ns
L3 interface delays in bypassed mode; LOWPWR = logic 1
t
pd1
propagation delay from
L3MODEM to L3MODEC;
L3DATAM to L3DATAC;
L3CLKM to L3CLKC
propagation delay from
L3DATAM to L3DATAC;
L3CLKM to L3CLKC
propagation delay from
L3DATAM to L3DATAC;
L3MODEM to L3MODEC
35
ns
t
pd2
20
+4
ns
t
pd3
20
+4
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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