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參數(shù)資料
| 型號(hào)： | SAA2013 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Adaptive allocation and scaling for PASC coding in DCC systems |
| 中文描述： | 自適應(yīng)分配和戴納信貸混凝劑縮放系統(tǒng)編碼 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 137K |
| 代理商： | SAA2013 |
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May 1994
15
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SAA2013
E
XTENDED SETTINGS
This is a single byte transfer, valid during decode and encode. The sequence of operations is:
1.
Microcontroller reads status from SAA2013, waiting for the flag RTRE to be set.
2.
When RTRE is logic 1, the microcontroller writes address bit 0 is logic 0, bit 1 is logic 0.
3.
One byte of extended settings is clocked into the transit register (SAA2013).
4.
When it is possible (i.e. subject to RTRC being HIGH, and assuming that allocation or status is not waiting), the byte
is transferred from the transit register to the SAA2003.
handbook, full pagewidth
L3MODEC
MGB366
STATUS
BYTES
PEAK 1
HALT
PEAK 2
15.625 s
Fig.13 Peak data timing.
Fig.14 L3 interface timing; SAA2013 to SAA2003 (address mode).
handbook, full pagewidth
td3
td4
td5
td2
th1
L3MODEC
L3CLKC
L3DATAC
(ADAS-SFC)
MGB367
cL
t
cH
t
td1
th2
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